John-David Wellman
John-David Wellman
Verified email at us.ibm.com
Title
Cited by
Cited by
Year
Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
DM Brooks, P Bose, SE Schuster, H Jacobson, PN Kudva, ...
IEEE Micro 20 (6), 26-44, 2000
6122000
Environment for PowerPC microarchitecture exploration
M Moudgill, JD Wellman, JH Moreno
IEEE Micro 19 (3), 15-25, 1999
1491999
Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ...
US Patent 6,779,049, 2004
1072004
Method and apparatus for memory prefetching based on intra-page usage history
JH Moreno, JA Rivers, JD Wellman
US Patent 6,678,795, 2004
692004
Implementing instruction set architectures with non-contiguous register file specifiers
MK Gschwind, RK Montoye, B Olsson, JD Wellman
US Patent 7,793,081, 2010
662010
Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors
ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ...
US Patent 6,907,477, 2005
532005
Power-performance modeling and tradeoff analysis for a high end microprocessor
D Brooks, M Martonosi, JD Wellman, P Bose
International Workshop on Power-Aware Computer Systems, 126-136, 2000
502000
Implementing instruction set architectures with non-contiguous register file specifiers
MK Gschwind, RK Montoye, B Olsson, JD Wellman
US Patent 8,166,281, 2012
472012
Implementing instruction set architectures with non-contiguous register file specifiers
MK Gschwind, RK Montoye, B Olsson, JD Wellman
US Patent 7,421,566, 2008
452008
System and method of execution of register pointer instructions ahead of instruction issues
E Altman, MK Gschwind, JA Rivers, SW Sathaye, JD Wellman, V Zyuban
US Patent 7,496,733, 2009
332009
Implementing instruction set architectures with non-contiguous register file specifiers
MK Gschwind, RK Montoye, B Olsson, JD Wellman
US Patent 8,918,623, 2014
312014
Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture
E Altman, M Gschwind, D Prener, J Rivers, S Sathaye, JD Wellman, ...
US Patent App. 11/047,983, 2006
312006
Token based DMA
HP Hofstee, R Nair, JD Wellman
US Patent 6,820,142, 2004
302004
Control signal memoization in a multiple instruction issue microprocessor
ER Altman, MK Gschwind, JA Rivers, SW Sathaye, JD Wellman, ...
US Patent 8,151,092, 2012
292012
Phaser: Phased methodology for modeling the system-level effects of soft errors
JA Rivers, P Bose, P Kudva, JD Wellman, PN Sanda, EH Cannon, ...
IBM Journal of Research and Development 52 (3), 293-306, 2008
272008
Evaluating the communication performance of MPPs using synthetic sparse matrix multiplication workloads
EL Boyd, JD Wellman, SG Abraham, ES Davidson
Proceedings of the 7th international conference on Supercomputing, 240-250, 1993
271993
Transient cache storage with discard function for disposable data
ER Altman, MK Gschwind, RK Montoye, JA Rivers, SW Sathaye, ...
US Patent 7,461,209, 2008
262008
System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessor
P Kudva, DS Levitan, B Sinharoy, JD Wellman
US Patent App. 11/737,491, 2008
252008
Methods for generating code for an architecture encoding an extended register specification
MK Gschwind, RK Montoye, B Olsson, JD Wellman
US Patent 8,312,424, 2012
222012
Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching
JH Moreno, JA Rivers, JD Wellman
US Patent 6,711,651, 2004
222004
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