| 6.4 A 56Gb/s 7.7 mW/Gb/s PAM-4 wireline transceiver in 10nm FinFET using MM-CDR-based ADC timing skew control and low-power DSP with approximate multiplier BJ Yoo, DH Lim, H Pang, JH Lee, SY Baek, N Kim, DH Choi, YH Choi, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 122-124, 2020 | 46 | 2020 |
| 250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 m CMOS SY Lee, HR Lee, YH Kwak, WS Choi, BJ Yoo, D Shim, C Kim, DK Jeong IEEE journal of solid-state circuits 46 (11), 2560-2570, 2011 | 18 | 2011 |
| A 72-GS/s, 8-bit DAC-based wireline transmitter in 4-nm FinFET CMOS for 200+ Gb/s serial links TO Dickson, ZT Deniz, M Cochet, TJ Beukema, M Kossel, T Morf, YH Choi, ... IEEE Journal of Solid-State Circuits 58 (4), 1074-1086, 2022 | 13 | 2022 |
| A 0.25-m CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture H Jeong, BJ Yoo, C Han, SY Lee, KY Lee, S Kim, DK Jeong, W Kim IEEE journal of solid-state circuits 42 (6), 1318-1327, 2007 | 13 | 2007 |
| A 10-Gb/s optical receiver front-end with 5-mW transimpedance amplifier KS Park, BJ Yoo, MS Hwang, H Chi, HC Kim, JW Park, K Kim, DK Jeong 2010 IEEE Asian Solid-State Circuits Conference, 1-4, 2010 | 12 | 2010 |
| An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS AS Yonar, PA Francese, M Brändli, M Kossel, T Morf, JE Proesel, S Rylov, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 6 | 2022 |
| Linearization technique for binary phase detectors in a collaborative timing recovery circuit BJ Yoo, WR Bae, J Han, J Kim, DK Jeong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6 …, 2013 | 6 | 2013 |
| Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface W Bae, BJ Yoo, DK Jeong 2012 International SoC Design Conference (ISOCC), 49-52, 2012 | 6 | 2012 |
| A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs J Kim, S Ryu, B Yoo, H Kim, Y Choi, DK Jeong 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 754-757, 2012 | 6 | 2012 |
| A 4nm 32Gb/s 8Tb/s/mm Die-to-Die chiplet using NRZ single-ended transceiver with equalization schemes and training techniques K Seong, D Park, G Bae, H Lee, Y Suh, W Oh, H Lee, J Kim, T Lee, G Mo, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 114-116, 2023 | 5 | 2023 |
| A 500 MHz-to-1.2 GHz reset free delay locked loop for memory controller with hysteresis coarse lock detector HK Chi, MS Hwang, BJ Yoo, WJ Choe, TH Kim, YS Moon, DK Jeong JSTS: Journal of Semiconductor Technology and Science 11 (2), 73-79, 2011 | 4 | 2011 |
| A study on Multichannel Receivers with Enhanced Lane Expandability and Loop Linearity BJ Yoo Ph. D. dissertation, Dept. Elect. Eng., Seoul National Univ., Seoul, Korea, 2013 | 2 | 2013 |
| A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology W Bae, DK Jeong, BJ Yoo 17th International Symposium on Design and Diagnostics of Electronic …, 2014 | 1 | 2014 |
| 13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets K Seong, W Oh, H Lee, G Bae, Y Suh, H Lee, J Kim, E Kim, Y Kang, G Mo, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 250-252, 2024 | | 2024 |
| A Semi-digital and Multi-channel Constant Loop Bandwidth Bang-bang Clock and Data Recovery Circuit with a Pulse Generator W Bae, BJ Yoo, DK Jeong The Institute of Semiconductor Engineers, 1037-1040, 2013 | | 2013 |
| A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring BJ Yoo, HY Song, HK Chi, WR Bae, DK Jeong JSTS: Journal of Semiconductor Technology and Science 12 (4), 433-448, 2012 | | 2012 |
| A 500-MHz to 1.2-GHz Constant Loop Bandwidth PLL for a Memory Controller BJ Yoo, HK Chi, TH Kim, DK Jeong ” The Institute of Semiconductor Engineers, 748-751, 2010 | | 2010 |
| A Skew Compensation Circuit Design using a Digitally Controlled Delay Line SW Kim, HK Chi, BJ Yoo, DK Jeong The Institute of Semiconductor Engineers, 772-775, 2010 | | 2010 |
| Verilog Modeling for Verifying Systematic Operation of Memory Controller Physical Layer TH Kim, BJ Yoo, WY Shin, DK Jeong The Institute of Semiconductor Engineers, 1246-1249, 2010 | | 2010 |
| A 5-Gb/s Receiver with a Digitally Controlled DFE for high-speed communication over a backplane channel JD Han, BJ Yoo, DH Lim, KS Park, DK Jeong The Institute of Semiconductor Engineers, 457-458, 2008 | | 2008 |
