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Rahul Shrestha
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Parameterized posit arithmetic hardware generator
R Chaurasiya, J Gustafson, R Shrestha, J Neudorfer, S Nambiar, K Niyogi, ...
2018 IEEE 36th International Conference on Computer Design (ICCD), 334-341, 2018
1152018
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards
R Shrestha, RP Paily
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — I: REGULAR PAPERS 61 (9), 2699-2710, 2014
672014
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
S Kumawat, R Shrestha, N Daga, R Paily
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS I: REGULAR PAPERS 62 (5), 1421-1430, 2015
562015
Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network
RB Chaurasiya, R Shrestha
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS I: REGULAR PAPERS 66 (11), 4448-4461, 2019
382019
Reconfigurable & Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks
MS Murty, R Shrestha
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS II: EXPRESS BRIEFS 65 (8), 1039-1043, 2018
272018
Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network
RB Chaurasiya, R Shrestha
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS I: REGULAR PAPERS 67 (4), 1296-1309, 2020
232020
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation
MS Murty, R Shrestha
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, 69-74, 2016
172016
High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder
R Shrestha, A Sahoo
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS II: EXPRESS BRIEFS 66 (7), 1144-1148, 2018
162018
Embedded hardware prototype for gas detection and monitoring system in Android mobile platform
R Kurzekar, H Arora, R Shrestha
2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017
152017
PGMA: an algorithmic approach for multi-objective hardware software partitioning
N Govil, R Shrestha, SR Chowdhury
Microprocessors and Microsystems 54, 83-96, 2017
152017
A new VLSI architecture of next-generation QC-LDPC decoder for 5G new-radio wireless-communication standard
A Verma, R Shrestha
2020 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2020
142020
A new partially-parallel VLSI-architecture of quasi-cyclic LDPC decoder for 5G new-radio
A Verma, R Shrestha
2020 33rd International Conference on VLSI Design and 2020 19th …, 2020
142020
Multi‐standard high‐throughput and low‐power quasi‐cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards
VK Kanchetla, R Shrestha, R Paily
IET Circuits, Devices & Systems 10 (2), 111-120, 2016
142016
Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes
A Verma, R Shrestha
IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, 2022
132022
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network
RB Chaurasiya, R Shrestha
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 29 (4), 760-773, 2021
132021
Hardware implementation and VLSI design of spectrum sensor for next‐generation LTE‐A cognitive‐radio wireless network
MS Murty, R Shrestha
IET Circuits, Devices & Systems 12 (5), 542-550, 2018
122018
Design and implementation of a high speed map decoder architecture for turbo decoding
R Shrestha, R Paily
26th IEEE International Conference on VLSI Design (VLSID) and 12th …, 2013
122013
Area-Efficient and Scalable Data-Fusion based Cooperative Spectrum Sensor for Cognitive Radio
RB Chaurasiya, R Shrestha
IEEE TRANSACTIONS ON CIRCUITS & SYSTEMS II: EXPRESS BRIEFS, 2020
112020
High-throughput and high-speed polar-decoder VLSI-architecture for 5G new radio
R Shrestha, P Bansal, S Srinivasan
2019 32nd International Conference on VLSI Design and 2019 18th …, 2019
102019
High-speed and low-power VLSI-architecture for inexact speculative adder
R Shrestha
2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2017
102017
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