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James Laudon
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In-datacenter performance analysis of a tensor processing unit
NP Jouppi, C Young, N Patil, D Patterson, G Agrawal, R Bajwa, S Bates, ...
Proceedings of the 44th Annual International Symposium on Computer …, 2017
36402017
Memory consistency and event ordering in scalable shared-memory multiprocessors
K Gharachorloo, D Lenoski, J Laudon, P Gibbons, A Gupta, J Hennessy
[1990] Proceedings. The 17th Annual International Symposium on Computer …, 1990
17541990
The stanford dash multiprocessor
D Lenoski, J Laudon, K Gharachorloo, WD Weber, A Gupta, J Hennessy, ...
Computer 25 (3), 63-79, 1992
14581992
The SGI Origin: a ccNUMA highly scalable server
J Laudon, D Lenoski
ACM SIGARCH Computer Architecture News 25 (2), 241-251, 1997
12131997
The directory-based cache coherence protocol for the DASH multiprocessor
D Lenoski, J Laudon, K Gharachorloo, A Gupta, J Hennessy
[1990] Proceedings. The 17th Annual International Symposium on Computer …, 1990
9791990
Fair queuing memory systems
KJ Nesbit, N Aggarwal, J Laudon, JE Smith
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
4622006
The DASH prototype: Implementation and performance
D Lenoski, J Laudon, T Joe, D Nakahira, L Stevens, A Gupta, J Hennessy
[1992] Proceedings the 19th Annual International Symposium on Computer …, 1992
2761992
The DASH prototype: Logic overhead and performance
D Lenoski, J Laudon, T Joe, D Nakahira, L Stevens, A Gupta, J Hennessy
IEEE Transactions on Parallel and Distributed Systems 4 (1), 41-61, 1993
2681993
Virtual private caches
KJ Nesbit, J Laudon, JE Smith
Proceedings of the 34th annual international symposium on Computer …, 2007
2202007
Maximizing CMP throughput with mediocre cores
JD Davis, J Laudon, K Olukotun
14th International Conference on Parallel Architectures and Compilation …, 2005
1632005
Interleaving: A multithreading technique targeting multiprocessors and workstations
J Laudon, A Gupta, M Horowitz
ACM SIGPLAN Notices 29 (11), 308-318, 1994
1601994
Chip multiprocessor architecture: techniques to improve throughput and latency
K Olukotun, L Hammond, J Laudon
Synthesis Lectures on Computer Architecture 2 (1), 1-145, 2007
1442007
High memory capacity DIMM with data and state memory
JP Laudon, DE Lenoski, J Manton, ME Anderson
US Patent 6,049,476, 2000
1372000
Apparatus and method for profiling system events in a fine grain multi-threaded multi-core processor
N Kosche, JP Laudon, AR Talcott, S Patel, F Sajjadian
US Patent 8,762,951, 2014
1272014
Chip Placement with Deep Reinforcement Learning
A Mirhoseini, A Goldie, M Yazgan, J Jiang, E Songhori, S Wang, YJ Lee, ...
arXiv preprint arXiv:2004.10746, 2020
1262020
A graph placement methodology for fast chip design
A Mirhoseini, A Goldie, M Yazgan, JW Jiang, E Songhori, S Wang, YJ Lee, ...
Nature 594 (7862), 207-212, 2021
1192021
A domain-specific supercomputer for training deep neural networks
NP Jouppi, DH Yoon, G Kurian, S Li, N Patil, J Laudon, C Young, ...
Communications of the ACM 63 (7), 67-78, 2020
1032020
Directory-based coherence protocol allowing efficient dropping of clean-exclusive data
JP Laudon
US Patent 5,680,576, 1997
861997
Using windowed register file to checkpoint register state
JP Laudon, AR Talcott, S Patel, TS Suresh
US Patent App. 11/484,970, 2008
832008
Performance/watt: the new server focus
J Laudon
ACM SIGARCH Computer Architecture News 33 (4), 5-13, 2005
832005
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