| Analyzing hardware security properties of processors through model checking B Kumar, AK Jaiswal, VS Vineesh, R Shinde 2020 33rd International Conference on VLSI Design and 2020 19th …, 2020 | 12 | 2020 |
| LUT-based Circuit Approximation with Targeted Error Guarantees G U, Vinod, VS Vineesh, J T Tudu, M Fujita, V Singh 2020 IEEE 29th Asian Test Symposium (ATS), 2020 | 7 | 2020 |
| Enhanced Design Debugging with Assistance from Guidance-based Model Checking VS Vineesh, B Kumar, R Shinde, N Sharma, M Fujita, V Singh IEEE Transactions on Computer-Aided Design (TCAD) of Integrated Circuits and …, 2020 | 3 | 2020 |
| Identification of effective guidance hints for better design debugging by formal methods VS Vineesh, B Kumar, J Adhaduk VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 3 | 2019 |
| Enhancing Testbench Quality via Genetic Algorithm H Bhargav, VS Vineesh, B Kumar, V Singh 2021 IEEE 64th International Midwest Symposium on Circuits and Systems (MWSCAS), 2021 | 2 | 2021 |
| Orion: A technique to prune state space search directions for guidance-based formal verification VS Vineesh, B Kumar, R Shinde, A Jaiswal, H Bhargava, V Singh 2019 IEEE 28th Asian Test Symposium (ATS), 123-1235, 2019 | 2 | 2019 |
| Method for bug localisation V Singh, B Kumar, VS Vineesh US Patent App. 18/086,796, 2023 | | 2023 |
| Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs B Kumar, VS Vineesh, P Nemade, M Fujita IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | | 2022 |
| Aquila: A Methodology for Achieving Fine- grained Bug Localization during Design Verification R Shinde, B Kumar, VS Vineesh, V Singh 20th IEEE Workshop on RTL and High Level Testing (WRTLT), 2019 | | 2019 |
| Achieving full functional coverage for the forwarding unit of pipelined processors VS Vineesh, N Hage, B Karthik, V Singh 2017 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2017 | | 2017 |
Binod KumarIIT JodhpurVerified email at iitj.ac.in
