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Takuya Nakaike
Takuya Nakaike
Senior Research Staff Member, IBM Tokyo Research Laboratory
Verified email at jp.ibm.com - Homepage
Title
Cited by
Cited by
Year
Workload characterization for microservices
T Ueda, T Nakaike, M Ohara
2016 IEEE international symposium on workload characterization (IISWC), 1-10, 2016
1622016
Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8
T Nakaike, R Odaira, M Gaudet, MM Michael, H Tomari
ACM SIGARCH Computer Architecture News 43 (3S), 144-157, 2015
1292015
Transactional memory support in the IBM POWER8 processor
HQ Le, GL Guthrie, DE Williams, MM Michael, BG Frey, WJ Starke, C May, ...
IBM Journal of Research and Development 59 (1), 8: 1-8: 14, 2015
972015
Data processing and difference computation for generating addressing information
M Abe, T Koyanagi, K Ono, M Hori, T Nakaike
US Patent 7,530,014, 2009
672009
Hyperledger fabric performance characterization and optimization using goleveldb benchmark
T Nakaike, Q Zhang, Y Ueda, T Inagaki, M Ohara
2020 IEEE International Conference on Blockchain and Cryptocurrency (ICBC), 1-9, 2020
452020
Thread-level speculation on off-the-shelf hardware transactional memory
R Odaira, T Nakaike
2014 IEEE International Symposium on Workload Characterization (IISWC), 212-221, 2014
392014
Compiler and runtime techniques for software transactional memory optimization
P Wu, MM Michael, C von Praun, T Nakaike, R Bordawekar, HW Cain, ...
Concurrency and Computation: Practice and Experience 21 (1), 7-23, 2009
382009
Program optimizing apparatus, program optimizing method, and program optimizing article of manufacture
T Nakaike
US Patent 8,990,786, 2015
292015
Technique for allocating register to variable for compiling
T Inagaki, H Komatsu, T Nakaike, R Odaira
US Patent 8,266,603, 2012
262012
Method for generating document components and managing same
K Fukuda, T Nakaike, H Takagi, T Ito
US Patent 7,519,956, 2009
212009
Measuring execution time for program optimization
T Nakaike, H Komacou, S Kawano
US Patent 8,181,169, 2012
192012
Coloring-based coalescing for graph coloring register allocation
R Odaira, T Nakaike, T Inagaki, H Komatsu, T Nakatani
Proceedings of the 8th annual IEEE/ACM international symposium on Code …, 2010
172010
Lock elision for read-only critical sections in java
T Nakaike, MM Michael
ACM SIGPLAN Notices 45 (6), 269-278, 2010
152010
Program editing apparatus, program editing method, and program for splitting a program file
T Nakaike, G Kondoh, F Kitayama, S Hirose
US Patent 7,712,079, 2010
152010
Profile-based global live-range splitting
T Nakaike, T Inagaki, H Komatsu, T Nakatani
ACM SIGPLAN Notices 41 (6), 216-227, 2006
132006
Profile-based detection of layered bottlenecks
T Inagaki, Y Ueda, T Nakaike, M Ohara
Proceedings of the 2019 ACM/SPEC International Conference on Performance …, 2019
122019
Testing optimized binary modules
T Koju, T Nakaike
US Patent 9,563,547, 2017
122017
Method for obtaining execution frequency information on execution paths in control flow graph, and computer and computer program for obtaining the information
T Nakaike
US Patent 9,250,880, 2016
122016
Method for allowing exclusive access to shared data
T Inagaki, T Nakaike, T Ogasawara, T Suganuma
US Patent 8,386,720, 2013
122013
Information processing device and compiler
T Nakaike, H Komatsu, S Kawano
US Patent App. 11/255,027, 2006
112006
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