| The rocket chip generator K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016 | 767 | 2016 |
| Graphite: A distributed parallel simulator for multicores JE Miller, H Kasture, G Kurian, C Gruenwald, N Beckmann, C Celio, ... HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010 | 641 | 2010 |
| The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor C Celio, K Asanović, D Patterson http://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-167.pdf, 2015 | 260* | 2015 |
| The rocket chip generator. EECS Department K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17 4, 6-2, 2016 | 135 | 2016 |
| BOOMv2: an open-source out-of-order RISC-V core C Celio, PF Chiu, B Nikolic, DA Patterson, K Asanovic First Workshop on Computer Architecture Research with RISC-V (CARRV), 2017 | 115 | 2017 |
| Free-flow zone electrophoresis of peptides and proteins in PDMS microchip for narrow pI range sample prefractionation coupled with mass spectrometry YA Song, M Chan, C Celio, S Tannenbaum, J Wishnok, J Han Analytical chemistry, 2010 | 67 | 2010 |
| Strober: Fast and accurate sample-based energy simulation for arbitrary RTL D Kim, A Izraelevitz, C Celio, H Kim, B Zimmer, Y Lee, J Bachrach, ... ACM SIGARCH Computer Architecture News 44 (3), 128-139, 2016 | 47 | 2016 |
| Evaluation of RISC-V RTL with FPGA-accelerated simulation D Kim, C Celio, D Biancolin, J Bachrach, K Asanovic First Workshop on Computer Architecture Research with RISC-V, 2017 | 32 | 2017 |
| Broom: an open-source out-of-order processor with resilient low-voltage operation in 28-nm cmos C Celio, PF Chiu, K Asanović, B Nikolić, D Patterson IEEE Micro 39 (2), 52-60, 2019 | 31 | 2019 |
| DESSERT: Debugging RTL effectively with state snapshotting for error replays across trillions of cycles D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanović 2018 28th International Conference on Field Programmable Logic and …, 2018 | 28 | 2018 |
| A highly productive implementation of an out-of-order processor generator CP Celio University of California, Berkeley, 2017 | 26 | 2017 |
| The renewed case for the reduced instruction set computer: Avoiding isa bloat with macro-op fusion for risc-v C Celio, P Dabbelt, DA Patterson, K Asanović arXiv preprint arXiv:1607.02318, 2016 | 16 | 2016 |
| An out-of-order risc-v processor with resilient low-voltage operation in 28nm cmos PF Chiu, C Celio, K Asanović, D Patterson, B Nikolić 2018 IEEE Symposium on VLSI Circuits, 61-62, 2018 | 13 | 2018 |
| The Berkeley Out-of-Order Machine (BOOM) Design Specification C Celio, D Patterson, K Asanovic University of California, Berkeley, 2016 | 8 | 2016 |
| The sodor processor collection C Celio, E Love Software repository. Cited on page 6, 108-109, 2014 | 8 | 2014 |
| Debugging RISC-V processors with FPGA-accelerated RTL simulation in the FPGA cloud D Kim, C Celio, S Karandikar, D Biancolin, J Bachrach, K Asanovic Appears in the 2nd Workshop on Computer Architecture Research with RISC-V …, 2018 | 6 | 2018 |
| Graphite: a distributed parallel simulator for multicores N Beckmann, J Eastep, C Gruenwald III, G Kurian, H Kasture, JE Miller, ... | 6 | 2009 |
| Securing High-performance RISC-V Processors from Time Speculation C Celio, J Renau Esperanto Technologies, 2018 | 5 | 2018 |
| Riscv-boom documentation C Celio, J Zhao, A Gonzalez, B Korpan April, 2019 | 3 | 2019 |
| Cache resiliency techniques for a low-voltage RISC-V out-of-order processor in 28-nm CMOS PF Chiu, C Celio, K Asanović, B Nikolić, D Patterson IEEE Solid-State Circuits Letters 1 (12), 229-232, 2018 | 3 | 2018 |
