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| 23.2 a 1.1 V 1ynm 6.4 Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, high-speed SerDes and RX/TX equalization scheme D Kim, M Park, S Jang, JY Song, H Chi, G Choi, S Choi, J Kim, C Kim, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 380-382, 2019 | 27 | 2019 |
| A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm … KC Chun, YG Chu, JS Heo, TS Kim, S Kim, HK Yang, MJ Kim, CK Lee, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 206-208, 2018 | 23 | 2018 |
| A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13- CMOS Technology B Song, K Kim, J Lee, J Chung, Y Choi, J Burm IEEE Transactions on Circuits and Systems II: Express Briefs 61 (9), 646-650, 2014 | 22 | 2014 |
| Domain wall memory based convolutional neural networks for bit-width extendability and energy-efficiency J Chung, J Park, S Ghosh Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 21 | 2016 |
| Circuit and method for initializing an internal logic unit in a semiconductor memory device JI Chung, CH Do US Patent 7,586,350, 2009 | 16 | 2009 |
| Exploiting serial access and asymmetric read/write of domain wall memory for area and energy-efficient digital signal processor design J Chung, K Ramclam, J Park, S Ghosh IEEE Transactions on Circuits and Systems I: Regular Papers 63 (1), 91-102, 2015 | 15 | 2015 |
| Delay locked loop circuit JI Chung, H Choi US Patent 7,830,187, 2010 | 15 | 2010 |
| Multi-port memory device with serial input/output interface JI Chung, J Kim, CH Do, H Hur US Patent 7,701,800, 2010 | 15 | 2010 |
| Semiconductor memory device H Hur, CH Do, JB Ko, JI Chung US Patent 7,979,758, 2011 | 14 | 2011 |
| Multi-port memory device JI Chung US Patent 7,613,065, 2009 | 12 | 2009 |
| A 1.3–4-GHz quadrature-phase digital DLL using sequential delay control and reconfigurable delay line H Park, J Sim, Y Choi, J Choi, Y Kwon, S Park, G Park, J Chung, KM Kim, ... IEEE Journal of Solid-State Circuits 56 (6), 1886-1896, 2021 | 11 | 2021 |
| Overview of circuits, systems, and applications of spintronics S Ghosh, A Iyengar, S Motaman, R Govindaraj, JW Jang, J Chung, J Park, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (3 …, 2016 | 11 | 2016 |
| Delay locked loop circuit JI Chung, H Choi US Patent 8,040,169, 2011 | 10 | 2011 |
| Read operation of multi-port memory device J Kim, CH Do, JI Chung, JH Im US Patent 7,660,168, 2010 | 10 | 2010 |
| A 10 Gb/s 4-PAM transceiver with adaptive pre-emphasis S Yoo, D Yun, B Song, J Burm, J Chung, JH Chun 2011 International Symposium on Integrated Circuits, 258-261, 2011 | 9 | 2011 |
| Multi-port memory device with serial input/output interface JI Chung, J Kim, CH Do, H Hur US Patent 8,031,552, 2011 | 9 | 2011 |
| Phase detection circuit and synchronization circuit using the same YS Seo, JI Chung US Patent 8,749,281, 2014 | 8 | 2014 |
| Signal generation circuit synchronized with a clock signal and a semiconductor apparatus using the same SW Oh, JI Chung US Patent 10,886,927, 2021 | 7 | 2021 |
| Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers J Chung, W Choi, J Park, S Ghosh IEEE Access 8 (1), 19783 - 19798, 2020 | 7 | 2020 |
