Giacomo Buonanno
Giacomo Buonanno
Universitą Carlo Cattaneo - LIUC
Verified email at liuc.it - Homepage
Title
Cited by
Cited by
Year
Factors affecting ERP system adoption: A comparative analysis between SMEs and large companies
G Buonanno, P Faverio, F Pigni, A Ravarini, D Sciuto, M Tagliavini
Journal of Enterprise Information Management 18 (4), 384-426, 2005
595*2005
Exploring the use of ERP systems by SMEs
M Tagliavini, P Faverio, A Ravarini, F Pigni, G Buonanno, N Callaos
planning 12, 23, 2002
542002
Introduzione ai sistemi informatici
D Sciuto, G Buonanno, L Mari
McGraw-Hill education, 2014
29*2014
Information system check-up as a leverage for SME development
A Ravarini, M Tagliavini, G Buonanno, D Sciuto
Managing Information Technology in Small Business: Challenges and Solutions …, 2002
212002
How an" evolving" fault model improves the behavioral test generation
G Buonanno, F Ferrandi, L Ferrandi, F Fummi, D Sciuto
Proceedings Great Lakes Symposium on VLSI, 124-129, 1997
211997
ALADIN: a multilevel testability analyzer for VLSI system design
M Bombana, G Buonanno, P Cavalloro, F Ferrandi, D Sciuto, G Zaza
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (2), 157-171, 1994
191994
Hardware specification using the assertion language ASTRAL
G Buonanno, A Coen-Porisini, W Fornaciari
Proceedings of the Advanced Research Workshop on Correct Hardware Design …, 1991
161991
A multilevel testability assistant for VLSI design
M Bombana, G Buonanno, P Cavalloro, D Sciuto, G Zaza
Proceedings EURO-DAC'92: European Design Automation Conference, 258-263, 1992
151992
Static redundancy techniques for CMOS gates
C Bolchini, G Buonanno, D Sciuto, R Stefanelli
1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996
131996
A wafer level testability approach based on an improved scan insertion technique
C Bolchini, G Buonanno, F Ferrandi, D Sciuto, M Bombana, P Cavalloro
IEEE Transactions on Components, Packaging, and Manufacturing Technology …, 1995
111995
CMOS Fault Tolerant Architectures for Switch level Faults
C Bolchini, G Buonanno, D Sciuto, R Stefanelli
JOURNAL OF MICROELECTRONIC SYSTEMS INTEGRATION 3 (2), 121-139, 1995
111995
A CMOS fault tolerant architecture for switch-level faults
C Bolchini, G Buonanno, D Sciuto, R Stefanelli
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 10-18, 1994
111994
How Internet connected SMEs exploit the potential of the net
G Buonanno, A Ravarini
-, 1998
101998
An improved fault tolerant architecture at CMOS level
C Bolchini, G Buonanno, D Sciuto, R Stefanelli
Proceedings of 1997 IEEE International Symposium on Circuits and Systems …, 1997
101997
A high-level synthesis approach to design of fault-tolerant systems
G Buonanno, M Pugassi, MG Sami
Proceedings. 15th IEEE VLSI Test Symposium (Cat. No. 97TB100125), 356-361, 1997
101997
Transistor stuck-at and delay faults detection in static and dynamic CMOS combinational gates
L Bruni, G Buonanno, D Sciuto
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems 1 …, 1992
101992
ICT diffusion and strategic role within Italian SMEs
G Buonanno, S Gramignoli, A Ravarini, M Tagliavini, D Sciuto
Global perspective of information technology management, 163-178, 2002
92002
An extended-UIO-based method for protocol conformance testing
G Buonanno, F Fummi, D Sciuto
Journal of systems architecture 46 (3), 225-242, 2000
92000
ICT Diffusion and Strategic Role
G Buonanno, S Gramignoli, A Ravarini, M Tagliavini
Challenges of Information Technology Management in the 21st Century: 2000 …, 2000
9*2000
Empirically testing the impact of ICT on business performance within SMEs
M Tagliavini, F Pigni, A Ravarini, G Buonanno
11th Annual Business IT Management Conference: Constructing IS Futures …, 2001
82001
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