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Alessio Spessot
Alessio Spessot
Verified email at imec.be
Title
Cited by
Cited by
Year
Method for tuning the effective work function of a gate structure in a semiconductor device
T Kauerauf, A Spessot, C Caillat
US Patent 9,076,726, 2015
3082015
Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017
2212017
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
1192018
Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration
H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ...
2017 IEEE international electron devices meeting (IEDM), 37.4. 1-37.4. 4, 2017
1182017
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
982017
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019
892019
1T-1C dynamic random access memory status, challenges, and prospects
A Spessot, H Oh
IEEE Transactions on Electron Devices 67 (4), 1382-1393, 2020
882020
Fabrication by electron beam induced deposition and transmission electron microscopic characterization of sub-10-nm freestanding Pt nanowires
S Frabboni, GC Gazzadi, L Felisari, A Spessot
Applied physics letters 88 (21), 2006
852006
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ...
2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016
752016
Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node
S Sakhare, M Perumkunnil, TH Bao, S Rao, W Kim, D Crotti, F Yasin, ...
2018 IEEE International Electron Devices Meeting (IEDM), 18.3. 1-18.3. 4, 2018
662018
Future logic scaling: Towards atomic channels and deconstructed chips
SB Samavedam, J Ryckaert, E Beyne, K Ronse, N Horiguchi, Z Tokei, ...
2020 IEEE International Electron Devices Meeting (IEDM), 1.1. 1-1.1. 10, 2020
632020
Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm
D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ...
2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019
622019
First monolithic integration of 3d complementary fet (cfet) on 300mm wafers
S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ...
2020 Ieee Symposium on Vlsi Technology, 1-2, 2020
592020
Role of mechanical stress in the resistance drift of Ge2Sb2Te5 films and phase change memories
M Rizzi, A Spessot, P Fantini, D Ielmini
Applied Physics Letters 99 (22), 2011
522011
Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels
E Bury, B Kaczer, D Linten, L Witters, H Mertens, N Waldron, X Zhou, ...
2016 IEEE International Electron Devices Meeting (IEDM), 15.6. 1-15.6. 4, 2016
482016
DTCO including sustainability: Power-performance-area-cost-environmental score (PPACE) analysis for logic technologies
MG Bardon, P Wuytens, LÅ Ragnarsson, G Mirabelli, D Jang, G Willems, ...
2020 IEEE International Electron Devices Meeting (IEDM), 41.4. 1-41.4. 4, 2020
472020
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
P Weckx, J Ryckaert, V Putcha, A De Keersgieter, J Boemmels, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2017
472017
TEM study of annealed Pt nanostructures grown by electron beam-induced deposition
S Frabboni, GC Gazzadi, A Spessot
Physica E: Low-dimensional Systems and Nanostructures 37 (1-2), 265-269, 2007
442007
The FAST module: An add-on unit for driving commercial scanning probe microscopes at video rate and beyond
F Esch, C Dri, A Spessot, C Africh, G Cautero, D Giuressi, R Sergo, ...
Review of Scientific Instruments 82 (5), 2011
362011
Introducing 2D-FETs in device scaling roadmap using DTCO
Z Ahmed, A Afzalian, T Schram, D Jang, D Verreck, Q Smets, ...
2020 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2020
352020
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