Manish Pandey
Manish Pandey
Adjunct Professor, ECE Department at Carnegie Mellon University
Verified email at andrew.cmu.edu
Title
Cited by
Cited by
Year
Formal verification of content addressable memories using symbolic trajectory evaluation
M Pandey, R Raimi, RE Bryant, MS Abadir
Proceedings of the 34th annual Design Automation Conference, 167-172, 1997
821997
Formal verification of content addressable memories using symbolic trajectory evaluation
M Pandey, R Raimi, RE Bryant, MS Abadir
Proceedings of the 34th annual Design Automation Conference, 167-172, 1997
821997
Formal verification of PowerPC arrays using symbolic trajectory evaluation
M Pandey, R Raimi, DL Beatty, RE Bryant
33rd Design Automation Conference Proceedings, 1996, 649-654, 1996
581996
Method and mechanism for implementing electronic designs having power information specifications background
Q Wang, A Gupta, P Chen, C Chu, M Pandey, HC Tsai, S Bhatia, Y Chen, ...
US Patent 7,739,629, 2010
492010
Method and system for equivalence checking of a low power design
M Pandey, R Arora, CC Lin, HC Tsai, B Chandramouli, KY Khoo
US Patent 7,669,165, 2010
382010
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
M Pandey, RE Bryant
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
361999
PowerPC/sup (TM)/array verification methodology using formal techniques
N Ganguly, M Abadir, M Pandey
Proceedings International Test Conference 1996. Test and Design Validity …, 1996
351996
Method and system for verifying power specifications of a low power design
B Chandramouli, HC Tsai, M Pandey, CC Lin, MM Das
US Patent 7,694,251, 2010
312010
Method and system for generating design constraints
M Pandey, M Glusman, A Krstic, YW Hsieh, A Lin
US Patent 7,962,886, 2011
282011
Managing model checks of sequential designs
J Yu, M Pandey
US Patent App. 10/140,403, 2018
24*2018
Built-in self-test structures around cellular automata and counters
AK Das, M Pandey, A Gupta, PP Chaudhuri
IEE Proceedings E (Computers and Digital Techniques) 137 (4), 269-276, 1990
191990
Formal verification of memory arrays
M Pandey
Carnegie Mellon University, 1997
181997
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
M Pandey, RE Bryant
International Conference on Computer Aided Verification, 244-255, 1997
171997
Method and system for logic equivalence checking
M Pandey, YT Lai, B Siarkowski, KY Khoo, CC Lin
US Patent 7,266,790, 2007
152007
Enhanced symbolic simulation for efficient verification of embedded array systems
T Feng, LC Wang, KT Cheng, M Pandey, MS Abadir
Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003
142003
Formal verification of memory arrays using symbolic trajectory evaluation
M Pandey, RE Bryant
Proceedings. International Workshop on Memory Technology, Design and Testing …, 1997
141997
Extraction of finite state machines from transistor netlists by symbolic simulation
M Pandey, A Jain, RE Bryant, D Beatty, G York, S Jain
Proceedings of ICCD'95 International Conference on Computer Design. VLSI in …, 1995
111995
Verifying multiple constraints for circuit designs
SC Ku, M Glusman, YW Hsieh, M Pandey, A Krstic, S Kirihennedige
US Patent 8,209,648, 2012
92012
Method and system for global coverage analysis
B Siarkowski, M Pandey
US Patent 7,587,690, 2009
92009
Method and system for generating design constraints
M Pandey, M Glusman, A Krstic, YW Hsieh, A Lin
US Patent 8,627,249, 2014
82014
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