José A Tierno
José A Tierno
Scientist, Apple Inc.
Verified email at
Cited by
Cited by
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
J Seo, B Brezzo, Y Liu, BD Parker, SK Esser, RK Montoye, B Rajendran, ...
2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011
A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI
JA Tierno, AV Rylyakov, DJ Friedman
IEEE Journal of Solid-State Circuits 43 (1), 42-51, 2008
Active management of timing guardband to save energy in POWER7
CR Lefurgy, AJ Drake, MS Floyd, MS Allen-Ware, B Brock, JA Tierno, ...
proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
Integrated transversal equalizers in high-speed fiber-optic systems
H Wu, JA Tierno, P Pepeljugoski, J Schaub, S Gowda, JA Kash, A Hajimiri
IEEE Journal of Solid-State Circuits 38 (12), 2131-2137, 2003
Introducing the adaptive energy management features of the power7 chip
M Floyd, M Allen-Ware, K Rajamani, B Brock, C Lefurgy, AJ Drake, ...
IEEE Micro 31 (2), 60-75, 2011
Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices
DJ Friedman, S Kim, CH Lam, DS Modha, B Rajendran, JA Tierno
US Patent 9,269,042, 2016
A 19-Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45-nm SOI CMOS
A Agrawal, JF Bulzacchelli, TO Dickson, Y Liu, JA Tierno, DJ Friedman
IEEE journal of solid-state circuits 47 (12), 3220-3231, 2012
Reconfigurable and customizable general-purpose circuits for neural networks
BV Brezzo, L Chang, SK Esser, DJ Friedman, Y Liu, DS Modha, ...
US Patent 8,856,055, 2014
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, JO Plouchart, AV Rylyakov, ...
IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
S Asaad, R Bellofatto, B Brezzo, C Haymes, M Kapur, B Parker, T Roewer, ...
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
A Rylyakov, J Tierno, H Ainspan, JO Plouchart, J Bulzacchelli, ZT Deniz, ...
2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009
An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz
M Singh, JA Tierno, A Rylyakov, S Rylov, SM Nowick
IEEE transactions on very large scale integration (VLSI) systems 18 (7 …, 2009
Active guardband management in power7+ to save energy and maintain reliability
CR Lefurgy, AJ Drake, MS Floyd, MS Allen-Ware, B Brock, JA Tierno, ...
IEEE Micro 33 (4), 35-45, 2013
A 100-MIPS GaAs asynchronous microprocessor
JA Tierno, AJ Martin, D Borkovic, TK Lee
IEEE Design & Test of Computers 11 (2), 43-49, 1994
A 28 ghz hybrid pll in 32 nm soi cmos
M Ferriss, A Rylyakov, JA Tierno, H Ainspan, DJ Friedman
IEEE Journal of Solid-State Circuits 49 (4), 1027-1035, 2014
A 7-tap transverse analog-FIR filter in 0.12/spl mu/m CMOS for equalization of 10Gb/s fiber-optic data systems
S Reynolds, P Pepeljugoski, J Schaub, J Tierno, D Beisser
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005
Adaptive energy-management features of the IBM POWER7 chip
M Floyd, M Ware, K Rajamani, T Gloekler, B Brock, P Bose, ...
IBM Journal of Research and Development 55 (3), 8: 1-8: 18, 2011
Methods and apparatus for timing recovery from a sampled and equalized data signal
JA Tierno
US Patent 6,650,699, 2003
Phase and frequency detector with output proportional to frequency difference
DJ Friedman, AV Rylyakov, JA Tierno
US Patent 8,222,936, 2012
An integral path self-calibration scheme for a dual-loop PLL
M Ferriss, JO Plouchart, A Natarajan, A Rylyakov, B Parker, JA Tierno, ...
IEEE Journal of Solid-State Circuits 48 (4), 996-1008, 2013
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