| A gate-level simulation environment for alpha-particle-induced transient faults H Cha, EM Rudnick, JH Patel, RK Iyer, GS Choi IEEE Transactions on Computers 45 (11), 1248-1256, 1996 | 176 | 1996 |
| VLSI architectures for layered decoding for irregular LDPC codes of WiMax KK Gunnam, GS Choi, MB Yeary, M Atiquzzaman 2007 IEEE International Conference on Communications, 4542-4547, 2007 | 154 | 2007 |
| Multi-rate layered decoder architecture for block LDPC codes of the IEEE 802.11 n wireless standard K Gunnam, G Choi, W Wang, M Yeary 2007 IEEE International Symposium on Circuits and Systems, 1645-1648, 2007 | 150 | 2007 |
| FOCUS: An experimental environment for fault sensitivity analysis GS Choi, RK Iyer IEEE Transactions on Computers 41 (12), 1515-1526, 1992 | 144 | 1992 |
| Next Generation iterative LDPC solutions for magnetic recording storage KK Gunnam, GS Choi, MB Yeary, S Yang, Y Lee 2008 42nd Asilomar Conference on Signals, Systems and Computers, 1148-1152, 2008 | 105 | 2008 |
| A parallel VLSI architecture for layered decoding for array LDPC codes KK Gunnam, GS Choi, MB Yeary 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 102 | 2007 |
| Value-reuse properties of min-sum for GF (q) K Gunnam, GS Choi, MB Yeary dated Oct, 2006 | 97 | 2006 |
| A design approach for radiation-hard digital electronics R Garg, N Jayakumar, SP Khatri, G Choi Proceedings of the 43rd annual Design Automation Conference, 773-778, 2006 | 85 | 2006 |
| Decoding of quasi-cyclic LDPC codes using an on-the-fly computation KK Gunnam, GS Choi, W Wang, E Kim, MB Yeary 2006 Fortieth Asilomar Conference on Signals, Systems and Computers, 1192-1199, 2006 | 78 | 2006 |
| XJ-BP: Express journey belief propagation decoding for polar codes J Xu, T Che, G Choi 2015 IEEE Global Communications Conference (GLOBECOM), 1-6, 2015 | 63 | 2015 |
| An LDPC decoding schedule for memory access reduction K Gunnam, G Choi, M Yeary 2004 IEEE International Conference on Acoustics, Speech, and Signal …, 2004 | 62 | 2004 |
| Low-density parity-check decoder architecture for high throughput optical fiber channels A Selvarathinam, E Kim, G Choi Proceedings 21st International Conference on Computer Design, 520-525, 2003 | 55 | 2003 |
| A fast and accurate gate-level transient fault simulation environment H Cha, EM Rudnick, GS Choi, JH Patel, RK Iyer FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing …, 1993 | 55 | 1993 |
| Support vector machine based detection of drowsiness using minimum EEG features S Yu, P Li, H Lin, E Rohani, G Choi, B Shao, Q Wang 2013 International Conference on Social Computing, 827-835, 2013 | 51 | 2013 |
| Technical Note on Iterative LDPC Solutions for Turbo Equalization KK Gunnam, GS Choi, MB Yeary Texas A&M Technical Note, Department of ECE, Texas A&M University, College …, 2006 | 51 | 2006 |
| Simulated fault injection: A methodology to evaluate fault tolerant microprocessor architectures GS Choi, RK Iyer, VA Carreno IEEE Transactions on Reliability 39 (4), 486-491, 1990 | 51 | 1990 |
| A massively scaleable decoder architecture for low-density parity-check codes A Selvarathinam, G Choi, K Narayanan, A Prabhakar, E Kim 2003 IEEE International Symposium on Circuits and Systems (ISCAS) 2, II-II, 2003 | 48 | 2003 |
| A fault behavior model for an avionic microprocessor: A case study GS Choi, RK Iyer, R Saleh, V Carreno Dependable Computing for Critical Applications, 177-195, 1991 | 41 | 1991 |
| Circuit-level design approaches for radiation-hard digital electronics R Garg, N Jayakumar, SP Khatri, GS Choi IEEE transactions on very large scale integration (VLSI) systems 17 (6), 781-792, 2009 | 39 | 2009 |
| Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system VA Carreno, G Choi, RK Iyer | 39 | 1990 |
Sina PourjabarPhD, Computer Engineering, Texas A&M UniversityVerified email at tamu.edu
