| MOSFET with super-steep retrograded island H Zhu, E Leobandung, AC Mocuta, DM Mocuta US Patent 7,723,750, 2010 | 355 | 2010 |
| Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases H Chen, D Mocuta, R Murphy, S Bedell, D Sadana US Patent App. 10/751,207, 2005 | 354 | 2005 |
| Method of preventing surface roughening during hydrogen prebake of SiGe substrates H Chen, DM Mocuta, RJ Murphy, SW Bedell, DK Sadana US Patent 6,958,286, 2005 | 303 | 2005 |
| Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates H Mertens, R Ritzenthaler, A Hikavyy, MS Kim, Z Tao, K Wostyn, SA Chew, ... 2016 IEEE symposium on VLSI technology, 1-2, 2016 | 209 | 2016 |
| Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates H Mertens, R Ritzenthaler, A Chasin, T Schram, E Kunnen, A Hikavyy, ... 2016 IEEE International Electron Devices Meeting (IEDM), 19.7. 1-19.7. 4, 2016 | 162 | 2016 |
| The Complementary FET (CFET) for CMOS scaling beyond N3 J Ryckaert, P Schuddinck, P Weckx, G Bouche, B Vincent, J Smith, ... 2018 IEEE Symposium on Vlsi Technology, 141-142, 2018 | 159 | 2018 |
| Structure and method for manufacturing MOSFET with super-steep retrograded island H Zhu, E Leobandung, AC Mocuta, DM Mocuta US Patent 7,268,049, 2007 | 135 | 2007 |
| High performance CMOS device structure with mid-gap metal gate AC Mocuta, M Ieong, RS Amos, DC Boyd, DM Mocuta, H Chen US Patent 6,916,698, 2005 | 132 | 2005 |
| Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ... 2017 IEEE international electron devices meeting (IEDM), 37.4. 1-37.4. 4, 2017 | 127 | 2017 |
| Strained Si CMOS (SS CMOS) technology: opportunities and challenges K Rim, R Anderson, D Boyd, F Cardone, K Chan, H Chen, S Christansen, ... Solid-State Electronics 47 (7), 1133-1139, 2003 | 124 | 2003 |
| Chemical treatment to retard diffusion in a semiconductor overlayer KK Chan, H Chen, MA Gribelyuk, JR Holt, WH Lee, RM Mitchell, RT Mo, ... US Patent 7,071,103, 2006 | 122 | 2006 |
| Impact of Wire Geometry on Interconnect RC and Circuit Delay I Ciofi, A Contino, PJ Roussel, R Baert, VH Vega-Gonzalez, K Croes, ... IEEE Transactions on Electron Devices 63 (6), 2488-2496, 2016 | 104 | 2016 |
| Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain D Chidambarrao, AC Mocuta, DM Mocuta, C Radens US Patent 7,691,698, 2010 | 100 | 2010 |
| RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology B Walsh, H Utomo, E Leobandung, A Mahorowala, D Mocuta, K Miyamoto, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 170-171, 2006 | 95 | 2006 |
| Test Structure and e-Beam Inspection Methodology for In-line Detection of (Non-visual) Missing Spacer Defects OD Patterson, K Wu, D Mocuta, K Nafisi 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 48-53, 2007 | 91 | 2007 |
| Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced vertical nanowires separation, new work function metal gate solutions, and DC/AC performance … R Ritzenthaler, H Mertens, V Pena, G Santoro, A Chasin, K Kenis, ... 2018 IEEE International Electron Devices Meeting (IEDM), 21.5. 1-21.5. 4, 2018 | 88 | 2018 |
| High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E Leobandung, H Nayakama, D Mocuta, K Miyamoto, M Angyal, HV Meer, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 126-127, 2005 | 85 | 2005 |
| Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom? K Ishikawa, K Karahashi, T Ishijima, SI Cho, S Elliott, D Hausmann, ... Japanese Journal of Applied Physics 57 (6S2), 06JA01, 2018 | 82 | 2018 |
| Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition L Witters, H Arimura, F Sebaai, A Hikavyy, AP Milenin, R Loo, ... IEEE transactions on electron devices 64 (11), 4587-4593, 2017 | 81 | 2017 |
| Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ... 2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016 | 78 | 2016 |
Nadine CollaertimecПодтвержден адрес электронной почты в домене imec.be
