Univ Rennes, INSA Rennes, IETR, CNRS UMR6164
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Preesm: A dataflow-based rapid prototyping framework for simplifying multicore dsp programming
M Pelcat, K Desnos, J Heulot, C Guy, JF Nezan, S Aridhi
2014 6th european embedded design in education and research conference …, 2014
Pimm: Parameterized and interfaced dataflow meta-model for mpsocs runtime reconfiguration
K Desnos, M Pelcat, JF Nezan, SS Bhattacharyya, S Aridhi
2013 International Conference on Embedded Computer Systems: Architectures …, 2013
Porting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architecture
R Lazcano, D Madroñal, R Salvador, K Desnos, M Pelcat, R Guerra, ...
Journal of Systems Architecture 77, 101-111, 2017
Spider: A synchronous parameterized and interfaced dataflow-based rtos for multicore dsps
J Heulot, M Pelcat, K Desnos, JF Nezan, S Aridhi
2014 6th European Embedded Design in Education and Research Conference …, 2014
Reproducible evaluation of system efficiency with a model of architecture: From theory to practice
M Pelcat, A Mercat, K Desnos, L Maggiani, Y Liu, J Heulot, JF Nezan, ...
IEEE transactions on computer-aided design of integrated circuits and …, 2017
Memory analysis and optimized allocation of dataflow applications on shared-memory mpsocs
K Desnos, M Pelcat, JF Nezan, S Aridhi
Journal of Signal Processing Systems 80 (1), 19-37, 2015
Automatic instrumentation of dataflow applications using PAPI
D Madroñal, A Morvan, R Lazcano, R Salvador, K Desnos, E Juárez, ...
Proceedings of the 15th ACM International Conference on Computing Frontiers …, 2018
Study of the impact of standard image compression techniques on performance of image classification with a convolutional neural network
M Dejean-Servières, K Desnos, K Abdelouahab, W Hamidouche, L Morin, ...
INSA Rennes; Univ Rennes; IETR; Institut Pascal, 2017
Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC
L Suriano, A Rodriguez, K Desnos, M Pelcat, E de la Torre
2017 12th International Symposium on Reconfigurable Communication-centric …, 2017
On exploiting energy-aware scheduling algorithms for mde-based design space exploration of mp2soc
M Ammar, M Baklouti, M Pelcat, K Desnos, M Abid
2016 24th Euromicro International Conference on Parallel, Distributed, and …, 2016
Papify: Automatic instrumentation and monitoring of dynamic dataflow applications based on papi
D Madronal, F Arrestier, J Sancho, A Morvan, R Lazcano, K Desnos, ...
IEEE Access 7, 111801-111812, 2019
Hardware/software self-adaptation in CPS: the CERBERO project approach
F Palumbo, T Fanni, C Sau, A Rodríguez, D Madroñal, K Desnos, ...
International Conference on Embedded Computer Systems, 416-428, 2019
On memory reuse between inputs and outputs of dataflow actors
K Desnos, M Pelcat, JF Nezan, S Aridhi
ACM Transactions on Embedded Computing Systems (TECS) 15 (2), 1-25, 2016
Efficient multicore implementation of an advanced generator of discrete chaotic sequences
K Desnos, S El Assad, A Arlicot, M Pelcat, D Menard
The 9th International Conference for Internet Technology and Secured …, 2014
Cerbero: Cross-layer model-based framework for multi-objective design of reconfigurable systems in uncertain hybrid environments: Invited paper: Cerbero teams from uniss, unica …
F Palumbo, T Fanni, C Sau, L Pulina, L Raffo, M Masin, E Shindin, ...
Proceedings of the 16th ACM International Conference on Computing Frontiers …, 2019
Scheduling of parallelized synchronous dataflow actors for multicore signal processing
Z Zhou, W Plishker, SS Bhattacharyya, K Desnos, M Pelcat, JF Nezan
Journal of Signal Processing Systems 83 (3), 309-328, 2016
Hierarchical dataflow model for efficient programming of clustered manycore processors
J Hascoët, K Desnos, JF Nezan, BD de Dinechin
2017 IEEE 28th International Conference on Application-specific Systems …, 2017
Parallelism Exploitation of a Dimensionality Reduction Algorithm Applied to Hyperspectral Images
R Lazcano, D Madroñal, K Desnos, M Pelcat, R Guerra, S López, ...
Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Scheduling of parallelized synchronous dataflow actors
Z Zhou, K Desnos, M Pelcat, JF Nezan, W Plishker, SS Bhattacharyya
2013 International Symposium on System on Chip (SoC), 1-10, 2013
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators
C Rubattu, F Palumbo, C Sau, R Salvador, J Sérot, K Desnos, L Raffo, ...
IEEE Embedded Systems Letters 11 (3), 69-72, 2018
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