Kimon Karras
Kimon Karras
Analog Devices
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Achieving 10Gbps Line-rate Key-value Stores with {FPGAs}
M Blott, K Karras, L Liu, K Vissers, J Bšr, Z IstvŠn
5th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 13), 2013
Scalable 10Gbps TCP/IP stack architecture for reconfigurable hardware
D Sidler, G Alonso, M Blott, K Karras, K Vissers, R Carley
2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom†…, 2015
Computing, caching, and communication at the edge: The cornerstone for building a versatile 5G ecosystem
EK Markakis, K Karras, A Sideris, G Alexiou, E Pallis
IEEE Communications Magazine 55 (11), 152-157, 2017
Ad-hoc routing protocol for aeronautical mobile ad-hoc networks
M Iordanakis, D Yannis, K Karras, G Bogdos, G Dilintas, M Amirfeiz, ...
Fifth international symposium on communication systems, networks and digital†…, 2006
Aeronautical mobile ad hoc networks
K Karras, T Kyritsis, M Amirfeiz, S Baiotti
2008 14th European Wireless Conference, 1-6, 2008
EXEGESIS: Extreme edge resource harvesting for a virtualized fog environment
EK Markakis, K Karras, N Zotos, A Sideris, T Moysiadis, A Corsaro, ...
IEEE Communications Magazine 55 (7), 173-179, 2017
Scaling Out to a {Single-Node} 80Gbps Memcached Server with 40Terabytes of Memory
M Blott, L Liu, K Karras, K Vissers
7th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage 15), 2015
Packet processing at 100 Gbps and beyond-challenges and perspectives
S Hauger, T Wild, A Mutter, A Kirstaedter, K Karras, R Ohlendorf, F Feller, ...
2009 ITG Symposium on Photonic Networks, 1-10, 2009
A hardware acceleration platform for AI-based inference at the edge
K Karras, E Pallis, G Mastorakis, Y Nikoloudakis, JM Batalla, ...
Circuits, Systems, and Signal Processing 39 (2), 1059-1070, 2020
Virtualization of programmable integrated circuits
K Karras, M Blott, KA Vissers
US Patent 9,503,093, 2016
Design space exploration of LDPC decoders using high-level synthesis
J Andrade, N George, K Karras, D Novo, F Pratas, L Sousa, P Ienne, ...
IEEE Access 5, 14600-14615, 2017
A folded pipeline network processor architecture for 100 Gbit/s networks
K Karras, T Wild, A Herkersdorf
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking†…, 2010
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
J Andrade, N George, K Karras, D Novo, V Silva, P Ienne, G Falc„o
2015 25th International Conference on Field Programmable Logic and†…, 2015
High-level synthesis case study: Implementation of a memcached server
K Karras, M Blott, K Vissers
arXiv preprint arXiv:1408.5387, 2014
Fast design space exploration using vivado HLS: Non-binary LDPC decoders
J Andrade, N George, K Karras, D Novo, V Silva, P Ienne, G Falcao
2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom†…, 2015
Accelerating packet buffering and administration in network processors
D Llorente, K Karras, M Meitinger, H Rauchfuss, T Wild, A Herkersdorf
2007 International Symposium on Integrated Circuits, 373-377, 2007
Designing protocol processing systems with Vivado high-level synthesis
K Karras, J Hrica
Xilinx application note XAPP1209(v1. 0.1), 2014
A cloud acceleration platform for edge and cloud
K Karras, O Kipouridis, N Zotos, E Markakis, G Bogdos
EnESCE: Wksp. Energy-Efficient Servers for Cloud and Edge Computing, 23-25, 2017
Improving memory subsystem performance in network processors with smart packet segmentation
K Karras, D Llorente, T Wild, A Herkersdorf
2008 International Conference on Embedded Computer Systems: Architectures†…, 2008
An embedded dynamically self-reconfigurable master-slaves mpsoc architecture
K Karras, ES Manolakos
2008 international conference on field programmable logic and applications†…, 2008
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