Patel Vrajesh - Google Scholar

Get my own profile

Cited by

	All	Since 2019
Citations	4	4
h-index	1	1
i10-index	0	0

0

4

2

202320241 3

Public access

1 article

1 article

available

not available

Based on funding mandates

Co-authors

Tom GlintResearch ScholarVerified email at iitgn.ac.in
Joycee MekieIIT GANDHINAGARVerified email at iitgn.ac.in
Kailash PrasadPhD Scholar in Electrical Engineering, Indian Institute of Technology GandhinagarVerified email at iitgn.ac.in

Patel Vrajesh

Patel Vrajesh

Student, Indian Institute of Technology Gandhinagar

Verified email at iitgn.ac.in

Computer Architecture DNN Accelerators


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Hardware-software codesign of dnn accelerators using approximate posit multipliers T Glint, K Prasad, J Dagli, K Gandhi, A Gupta, V Patel, N Shah, J Mekie Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023	4	2023
COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators V Patel, N Shah, A Krishna, T Glint, A Ronak, J Mekie 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024		2024
Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA T Glint, A Gupta, D Giftson, G Shah, V Patel, R Chudasama, S More, ... 2023 IEEE International Symposium on Performance Analysis of Systems and …, 2023		2023

The system can't perform the operation now. Try again later.

Articles 1–3