A Batteryless 19 W MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications Y Zhang, F Zhang, Y Shakhsheer, JD Silver, A Klinefelter, M Nagaraju, ...
IEEE Journal of Solid-State Circuits 48 (1), 199-213, 2012
424 2012 Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
367 2019 A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC F Zhang, Y Zhang, J Silver, Y Shakhsheer, M Nagaraju, A Klinefelter, ...
2012 IEEE International Solid-State Circuits Conference, 298-300, 2012
166 2012 21.3 A 6.45 μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios A Klinefelter, NE Roberts, Y Shakhsheer, P Gonzalez, A Shrivastava, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
127 2015 Magnet: A modular accelerator generator for neural networks R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
117 2019 Body sensor networks: A holistic approach from silicon to users BH Calhoun, J Lach, J Stankovic, DD Wentzloff, K Whitehouse, AT Barth, ...
Proceedings of the IEEE 100 (1), 91-106, 2011
114 2011 A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020
93 2020 GRANNITE: Graph neural network inference for transferable power estimation Y Zhang, H Ren, B Khailany
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
81 2020 A modular digital VLSI flow for high-productivity SoC design B Khailany, R Venkatesan, J Clemons, JS Emer, M Fojtik, A Klinefelter, ...
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
73 2018 PRIMAL: Power inference using machine learning Y Zhou, H Ren, Y Zhang, B Keller, B Khailany, Z Zhang
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
70 2019 Accelerating chip design with machine learning B Khailany
Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 33-33, 2020
69 2020 A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
2019 Symposium on VLSI Circuits, C300-C301, 2019
52 2019 A 0.6 V 8 pJ/write non-volatile CBRAM macro embedded in a body sensor node for ultra low energy applications N Gilbert, Y Zhang, J Dinh, B Calhoun, S Hollmer
2013 Symposium on VLSI Circuits, C204-C205, 2013
42 2013 Energy efficient design for body sensor nodes Y Zhang, Y Shakhsheer, AT Barth, HC Powell Jr, SA Ridenour, ...
Journal of Low Power Electronics and Applications 1 (1), 109-130, 2011
39 2011 FIST: A feature-importance sampling and tree-based method for automatic design flow parameter tuning Z Xie, GQ Fang, YH Huang, H Ren, Y Zhang, B Khailany, SY Fang, J Hu, ...
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 19-25, 2020
35 2020 System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms BH Calhoun, S Khanna, Y Zhang, J Ryan, B Otis
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
34 2010 From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus DL Lin, H Ren, Y Zhang, B Khailany, TW Huang
Proceedings of the 51st International Conference on Parallel Processing, 1-12, 2022
21 2022 MAVIREC: ML-aided vectored IR-drop estimation and classification VA Chhabria, Y Zhang, H Ren, B Keller, B Khailany, SS Sapatnekar
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
21 2021 Ultra low power sensing platform with multimodal radios BH Calhoun, Y Shakhsheer, Y Zhang, A Klinefelter, DD Wentzloff, ...
US Patent 9,729,189, 2017
20 2017 Hold time closure for subthreshold circuits using a two-phase, latch based timing method Y Zhang, BH Calhoun
2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2013
17 2013