Fangfei Liu
Title
Cited by
Cited by
Year
Last-level cache side-channel attacks are practical
F Liu, Y Yarom, Q Ge, G Heiser, RB Lee
IEEE Symposium on Security and Privacy, 605-622, 2015
8632015
CATalyst: Defeating Last-Level Cache Side Channel Attacks in Cloud Computing
F Liu, Q Ge, Y Yarom, F Mckeen, C Rozas, G Heiser, RB Lee
IEEE International Symposium on High Performance Computer Architecture (HPCA …, 2016
3152016
Random fill cache architecture
F Liu, RB Lee
Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium …, 2014
2092014
Compact optical temporal differentiator based on silicon microring resonator
F Liu, T Wang, L Qiang, T Ye, Z Zhang, M Qiu, Y Su
Optics Express 16 (20), 15880-15886, 2008
1932008
Mapping the Intel last-level cache
Y Yarom, Q Ge, F Liu, RB Lee, G Heiser
Cryptology ePrint Archive, Report 2015/905, 2015
972015
Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks
F Liu, H Wu, K Mai, RB Lee
IEEE Micro 36 (5), 8-16, 2016
712016
Optically tunable delay line in silicon microring resonator based on thermal nonlinear effect
F Liu, Q Li, Z Zhang, M Qiu, Y Su
Selected Topics in Quantum Electronics, IEEE Journal of 14 (3), 706-712, 2008
642008
Side channel vulnerability metrics: the promise and the pitfalls
T Zhang, F Liu, S Chen, RB Lee
Proceedings of the 2nd International Workshop on Hardware and Architectural …, 2013
362013
Security testing of a secure cache design
F Liu, RB Lee
Proceedings of the 2nd International Workshop on Hardware and Architectural …, 2013
332013
On-chip photonic generation of ultra-wideband monocycle pulses
F Liu, T Wang, Z Zhang, M Qiu, Y Su
Electronics letters 45 (24), 1, 2009
312009
Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses
S Chen, F Liu, Z Mi, Y Zhang, RB Lee, H Chen, XF Wang
Proceedings of the 2018 on Asia Conference on Computer and Communications …, 2018
202018
DPSK/FSK hybrid modulation format and analysis of its nonlinear performance
F Liu, Y Su
Journal of Lightwave Technology 26 (3), 357-364, 2008
192008
Can randomized mapping secure instruction caches from side-channel attacks?
F Liu, H Wu, RB Lee
Proceedings of the Fourth Workshop on Hardware and Architectural Support for …, 2015
82015
Speculative interference attacks: Breaking invisible speculation schemes
M Behnia, P Sahu, R Paccagnella, J Yu, ZN Zhao, X Zou, T Unterluggauer, ...
Proceedings of the 26th ACM International Conference on Architectural …, 2021
72021
Cloud Server Benchmark Suite for Evaluating New Hardware Architectures
H Wu, F Liu, RB Lee
IEEE Computer Architecture Letters 16 (1), 14-17, 2017
52017
Restricted speculative execution
R Gabor, A Alameldeen, A Basak, F Liu, F McKeen, J Nuzman, C Rozas, ...
US Patent App. 16/443,593, 2020
42020
A 32kB Secure Cache Memory with Dynamic Replacement Mapping in 65nm bulk CMOS
B Erbagci, F Liu, C Cakir, NEC Akkaya, R Lee, K Mai
IEEE Asian Solid-State Circuits Conference, 2015
32015
Hardware load hardening for speculative side-channel attacks
F Liu, A Alameldeen, A Basak, R Gabor, F McKeen, J Nuzman, C Rozas, ...
US Patent App. 16/458,006, 2020
12020
Processor instruction support to defeat side-channel attacks
F Liu, B Xing, M Steiner, M Vij, C Rozas, F McKeen, M Ozsoy, ...
US Patent App. 16/024,733, 2020
12020
Processor instruction support for mitigating controlled-channel and cache-based side-channel attacks
S Constable, F Liu, B Xing, M Steiner, M Vij, C Rozas, FX McKeen, ...
US Patent App. 16/458,015, 2020
2020
The system can't perform the operation now. Try again later.
Articles 1–20