| Learning-based approximation of interconnect delay and slew in signoff timing tools AB Kahng, S Kang, H Lee, S Nath, J Wadhwani 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2013 | 58 | 2013 |
| High-performance gate sizing with a signoff timer AB Kahng, S Kang, H Lee, IL Markov, P Thapar 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 450-457, 2013 | 44 | 2013 |
| Scalable detailed placement legalization for complex sub-14nm constraints K Han, AB Kahng, H Lee 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 867-873, 2015 | 37 | 2015 |
| Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router K Han, AB Kahng, H Lee Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 36 | 2015 |
| Timing margin recovery with flexible flip-flop timing model AB Kanng, H Lee Fifteenth International Symposium on Quality Electronic Design, 496-503, 2014 | 32 | 2014 |
| Horizontal benchmark extension for improved assessment of physical CAD research AB Kahng, H Lee, J Li Proceedings of the 24th edition of the great lakes symposium on VLSI, 27-32, 2014 | 30 | 2014 |
| Minimum implant area-aware gate sizing and placement AB Kahng, H Lee Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI, 57-62, 2014 | 23 | 2014 |
| Pulse width allocation and clock skew scheduling: Optimizing sequential circuits based on pulsed latches H Lee, S Paik, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 23 | 2010 |
| Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits H Lee, S Paik, Y Shin 2008 IEEE/ACM International Conference on Computer-Aided Design, 224-229, 2008 | 22 | 2008 |
| Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI C Han, K Han, AB Kahng, H Lee, L Wang, B Xu 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 667-674, 2017 | 19 | 2017 |
| Smart non-default routing for clock power reduction AB Kahng, S Kang, H Lee Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013 | 18 | 2013 |
| PROBE: A placement, routing, back-end-of-line measurement utility A Kahng, AB Kahng, H Lee, J Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 17 | 2017 |
| ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology K Han, AB Kahng, H Lee, L Wang Photomask Technology 2015 9635, 80-93, 2015 | 17 | 2015 |
| Vertical M1 routing-aware detailed placement for congestion and wirelength reduction in sub-10nm nodes P Debacker, K Han, AB Kahng, H Lee, P Raghavan, L Wang Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 15 | 2017 |
| Enhancing sensitivity-based power reduction for an industry IC design context H Fatemi, AB Kahng, H Lee, J Li, JP de Gyvez Integration 66, 96-111, 2019 | 14 | 2019 |
| Performance-and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes K Han, AB Kahng, H Lee, L Wang 2017 18th International Symposium on Quality Electronic Design (ISQED), 104-110, 2017 | 6 | 2017 |
| Measuring progress and value of IC implementation technology AB Kahng, H Lee, J Li 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 4 | 2016 |
| Heuristic methods for fine-grain exploitation of FDSOI H Fatemi, AB Kahng, H Lee, JP de Gyvez IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 3 | 2019 |
| MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts P Debacker, K Han, AB Kahng, H Lee, P Raghavan, L Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 1 | 2017 |
| Physical Design and Technology Optimizations for Advanced VLSI Manufacturing HI Lee University of California, San Diego, 2018 | | 2018 |
Lutong WangCadence Design Systems, Inc.Подтвержден адрес электронной почты в домене cadence.com
