| Speculative precomputation: Long-range prefetching of delinquent loads JD Collins, H Wang, DM Tullsen, C Hughes, YF Lee, D Lavery, JP Shen Proceedings 28th Annual International Symposium on Computer Architecture, 14-25, 2001 | 500 | 2001 |
| Hybrid transactional memory S Kumar, M Chu, CJ Hughes, P Kundu, A Nguyen Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006 | 386 | 2006 |
| Performance evaluation of IntelŽ transactional synchronization extensions for high-performance computing RM Yoo, CJ Hughes, K Lai, R Rajwar Proceedings of the International Conference on High Performance Computing …, 2013 | 375 | 2013 |
| Carbon: architectural support for fine-grained parallelism on chip multiprocessors S Kumar, CJ Hughes, A Nguyen ACM SIGARCH Computer Architecture News 35 (2), 162-173, 2007 | 366 | 2007 |
| RSIM: Simulating shared-memory multiprocessors with ILP processors CJ Hughes, VS Pai, P Ranganathan, SV Adve IEEE Computer 35 (2), 40-49, 2002 | 289 | 2002 |
| Saving energy with architectural and frequency adaptations for multimedia applications CJ Hughes, J Srinivasan, SV Adve Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001 | 218 | 2001 |
| Exploring simd for molecular dynamics, using intelŽ xeonŽ processors and intelŽ xeon phi coprocessors SJ Pennycook, CJ Hughes, M Smelyanskiy, SA Jarvis 2013 IEEE 27th International Symposium on Parallel and Distributed …, 2013 | 216 | 2013 |
| IMP: Indirect Memory Prefetcher X Yu, CJ Hughes, N Satish, S Devadas Proceedings of the 48th International Symposium on Microarchitecture, 178-190, 2015 | 196 | 2015 |
| Hybrid hardware and software implementation of transactional memory access S Kumar, CJ Hughes, P Kundu, A Nguyen US Patent 7,856,537, 2010 | 175* | 2010 |
| Convergence of recognition, mining, and synthesis workloads and its implications YK Chen, J Chhugani, P Dubey, CJ Hughes, D Kim, S Kumar, VW Lee, ... Proceedings of the IEEE 96 (5), 790-807, 2008 | 149 | 2008 |
| Soft real-time scheduling on simultaneous multithreaded processors R Jain, CJ Hughes, SV Adve 23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002., 134-145, 2002 | 135 | 2002 |
| Variability in the execution of multimedia applications and implications for architecture CJ Hughes, P Kaul, SV Adve, R Jain, C Park, J Srinivasan ACM SIGARCH Computer Architecture News 29 (2), 254-265, 2001 | 128 | 2001 |
| Hybrid hardware and software implementation of transactional memory access S Kumar, CJ Hughes, P Kundu, A Nguyen US Patent App. 15/477,055, 2017 | 124* | 2017 |
| Caching DAG traces H Wang, NA Chazin, CJ Hughes, R Kling, J Shen, YF Lee US Patent App. 09/823,235, 2001 | 116 | 2001 |
| Vector instructions to enable efficient synchronization and parallel reduction operations M Smelyanskiy, V Lee, C Hughes, D Kim, YK Chen, C Kim, J Chhugani, ... US Patent 9,678,750, 2017 | 103 | 2017 |
| Vector instructions to enable efficient synchronization and parallel reduction operations M Smelyanskiy, S Kumar, D Kim, J Chhugani, C Kim, CJ Hughes, VW Lee, ... US Patent 9,513,905, 2016 | 103 | 2016 |
| Joint local and global hardware adaptations for energy R Sasanka, CJ Hughes, SV Adve ACM SIGARCH Computer Architecture News 30 (5), 144-155, 2002 | 100 | 2002 |
| Vector instructions to enable efficient synchronization and parallel reduction operations M Smelyanskiy, S Kumar, D Kim, J Chhugani, C Kim, CJ Hughes, VW Lee, ... US Patent 9,513,905, 2016 | 97 | 2016 |
| Vector instructions to enable efficient synchronization and parallel reduction operations M Smelyanskiy, S Kumar, D Kim, J Chhugani, C Kim, CJ Hughes, VW Lee, ... US Patent App. 12/079,774, 2008 | 97* | 2008 |
| Banshee: Bandwidth-efficient DRAM caching via software/hardware cooperation X Yu, CJ Hughes, N Satish, O Mutlu, S Devadas Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 93 | 2017 |
Yen-Kuang ChenIntelVerified email at ieee.org
