Christopher Hughes
Christopher Hughes
Verified email at intel.com
Title
Cited by
Cited by
Year
Speculative precomputation: Long-range prefetching of delinquent loads
JD Collins, H Wang, DM Tullsen, C Hughes, YF Lee, D Lavery, JP Shen
Proceedings 28th Annual International Symposium on Computer Architecture, 14-25, 2001
4712001
Hybrid transactional memory
S Kumar, M Chu, CJ Hughes, P Kundu, A Nguyen
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006
3732006
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
S Kumar, CJ Hughes, A Nguyen
ACM SIGARCH Computer Architecture News 35 (2), 162-173, 2007
3212007
Performance evaluation of IntelŽ transactional synchronization extensions for high-performance computing
RM Yoo, CJ Hughes, K Lai, R Rajwar
Proceedings of the International Conference on High Performance Computing …, 2013
3152013
RSIM: Simulating shared-memory multiprocessors with ILP processors
CJ Hughes, VS Pai, P Ranganathan, SV Adve
IEEE Computer 35 (2), 40-49, 2002
2792002
Saving energy with architectural and frequency adaptations for multimedia applications
CJ Hughes, J Srinivasan, SV Adve
Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001
2092001
Exploring simd for molecular dynamics, using intelŽ xeonŽ processors and intelŽ xeon phi coprocessors
SJ Pennycook, CJ Hughes, M Smelyanskiy, SA Jarvis
2013 IEEE 27th International Symposium on Parallel and Distributed …, 2013
1892013
Hybrid hardware and software implementation of transactional memory access
S Kumar, CJ Hughes, P Kundu, A Nguyen
US Patent 7,856,537, 2010
172*2010
Convergence of recognition, mining, and synthesis workloads and its implications
YK Chen, J Chhugani, P Dubey, CJ Hughes, D Kim, S Kumar, VW Lee, ...
Proceedings of the IEEE 96 (5), 790-807, 2008
1412008
Soft real-time scheduling on simultaneous multithreaded processors
R Jain, CJ Hughes, SV Adve
23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002., 134-145, 2002
1282002
Hybrid hardware and software implementation of transactional memory access
S Kumar, CJ Hughes, P Kundu, A Nguyen
US Patent App. 15/477,055, 2017
123*2017
Variability in the execution of multimedia applications and implications for architecture
CJ Hughes, P Kaul, SV Adve, R Jain, C Park, J Srinivasan
ACM SIGARCH Computer Architecture News 29 (2), 254-265, 2001
1232001
Caching DAG traces
H Wang, NA Chazin, CJ Hughes, R Kling, J Shen, YF Lee
US Patent App. 09/823,235, 2001
1112001
IMP: Indirect Memory Prefetcher
X Yu, CJ Hughes, N Satish, S Devadas
Proceedings of the 48th International Symposium on Microarchitecture, 178-190, 2015
1022015
Joint local and global hardware adaptations for energy
R Sasanka, CJ Hughes, SV Adve
ACM SIGARCH Computer Architecture News 30 (5), 144-155, 2002
972002
Vector instructions to enable efficient synchronization and parallel reduction operations
M Smelyanskiy, V Lee, C Hughes, D Kim, YK Chen, C Kim, J Chhugani, ...
US Patent 9,678,750, 2017
962017
Vector instructions to enable efficient synchronization and parallel reduction operations
M Smelyanskiy, S Kumar, D Kim, J Chhugani, C Kim, CJ Hughes, VW Lee, ...
US Patent 9,513,905, 2016
962016
Vector instructions to enable efficient synchronization and parallel reduction operations
M Smelyanskiy, S Kumar, D Kim, J Chhugani, C Kim, CJ Hughes, VW Lee, ...
US Patent 9,513,905, 2016
912016
Vector instructions to enable efficient synchronization and parallel reduction operations
M Smelyanskiy, S Kumar, D Kim, J Chhugani, C Kim, CJ Hughes, VW Lee, ...
US Patent App. 12/079,774, 2008
91*2008
Systems, apparatuses, and methods for data speculation execution
E Ould-Ahmed-Vall, CJ Hughes, R Valentine, MB Girkar, H Ido, Y Wu, ...
US Patent 10,303,525, 2019
77*2019
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