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Binod Kumar
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A methodology for trace signal selection to improve error detection in post-silicon validation
B Kumar, A Jindal, V Singh, M Fujita
2017 30th International Conference on VLSI Design and 2017 16th …, 2017
172017
Post-silicon observability enhancement with topology based trace signal selection
B Kumar, A Jindal, M Fujita, V Singh
2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017
122017
Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications
V Kumar, A Singh, S Upadhyay, B Kumar
Journal of Circuits, Systems and Computers 28 (10), 1950171, 2019
112019
Rtl level trace signal selection and coverage estimation during post-silicon validation
B Kumar, K Basu, M Fujita, V Singh
2017 IEEE International High Level Design Validation and Test Workshop …, 2017
112017
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection
B Kumar, A Jindal, M Fujita, V Singh
Proceedings of the on Great Lakes Symposium on VLSI 2017, 191-196, 2017
112017
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs
NK Jha, S Mittal, B Kumar, G Mattela
ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (1), 1-25, 2020
92020
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection
B Kumar, K Basu, M Fujita, V Singh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
92018
Testing multiple stuck-at faults of robdd based combinational circuit design
T Shah, A Matrosova, B Kumar, M Fujita, V Singh
2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017
82017
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug
B Kumar, J Adhaduk, K Basu, M Fujita, V Singh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4 …, 2020
52020
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm
A Jindal, B Kumar, N Jindal, M Fujita, V Singh
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 46-51, 2018
52018
Improving post-silicon error detection with topological selection of trace signals
B Kumar, K Basu, A Jindal, M Fujita, V Singh
2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017
52017
Analyzing Hardware Security Properties of Processors through Model Checking
B Kumar, AK Jaiswal, VS Vineesh, R Shinde
2020 33rd International Conference on VLSI Design and 2020 19th …, 2020
42020
Performance modelling of heterogeneous ISA multicore architectures
NK Boran, RP Meghwal, K Sharma, B Kumar, V Singh
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
42016
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture
B Kumar, B Nehru, B Pandey, V Singh, J Tudu
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
42016
A trace signal selection algorithm for improved post-silicon debug
B Kumar, A Jindal, V Singh
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
42016
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking
VS Vineesh, B Kumar, R Shinde, N Sharma, M Fujita, V Singh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
32020
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability
B Kumar, AK Bhosale, M Fujita, V Singh
2019 IEEE 28th Asian Test Symposium (ATS), 99-995, 2019
32019
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods
VS Vineesh, B Kumar, J Adhaduk
International Symposium on VLSI Design and Test, 413-427, 2019
32019
Elura: a methodology for post-silicon gate-level error localization using regression analysis
A Jindal, B Kumar, K Basu, M Fujita
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
32018
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification
VS Vineesh, B Kumar, R Shinde, A Jaiswal, H Bhargava, V Singh
2019 IEEE 28th Asian Test Symposium (ATS), 123-1235, 2019
22019
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Articles 1–20