| Synthesis of active-mode power-gating circuits J Seomun, I Shin, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 27 | 2012 |
| HLS-l: A High-Level Synthesis framework for latch-based architectures S Paik, I Shin, T Kim, Y Shin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 21 | 2010 |
| Register allocation for high-level synthesis using dual supply voltages I Shin, S Paik, Y Shin Proceedings of the 46th Annual Design Automation Conference, 937-942, 2009 | 19 | 2009 |
| A pipeline architecture with 1-cycle timing error correction for low voltage operations I Shin, JJ Kim, YS Lin, Y Shin International Symposium on Low Power Electronics and Design (ISLPED), 199-204, 2013 | 17 | 2013 |
| Synthesis and implementation of active mode power gating circuits J Seomun, I Shin, Y Shin Proceedings of the 47th Design Automation Conference, 487-492, 2010 | 14 | 2010 |
| Aggressive voltage scaling through fast correction of multiple errors with seamless pipeline operation I Shin, JJ Kim, Y Shin IEEE Transactions on Circuits and Systems I: Regular Papers 62 (2), 468-477, 2015 | 13 | 2015 |
| HLS-dv: A high-level synthesis framework for dual-Vdd architectures I Shin, S Paik, D Shin, Y Shin IEEE transactions on very large scale integration (VLSI) systems 20 (4), 593-604, 2011 | 13 | 2011 |
| Voltage monitor for generating delay codes J Seomun, I Shin, K Do, JY Choi US Patent 9,984,732, 2018 | 10 | 2018 |
| One-cycle correction of timing errors in pipelines with standard clocked elements I Shin, JJ Kim, YS Lin, Y Shin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 600-612, 2015 | 8 | 2015 |
| Selectively patterned masks: Structured ASIC with asymptotically ASIC performance D Baek, I Shin, S Paik, Y Shin 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 376-381, 2011 | 8 | 2011 |
| Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling I Shin, JJ Kim, Y Shin 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 179-184, 2014 | 3 | 2014 |
| Accurate gate delay extraction for timing analysis of body-biased circuits D Baek, I Shin, Y Shin Journal of Circuits, Systems and Computers 22 (08), 1350072, 2013 | 2 | 2013 |
| Pulsed-latch based razor with 1-cycle error recovery scheme JJ Kim, YS Lin, I Shin US Patent 9,715,437, 2017 | 1 | 2017 |
| HLS-l: High-level synthesis of high performance latch-based circuits S Paik, I Shin, Y Shin 2009 Design, Automation & Test in Europe Conference & Exhibition, 1112-1117, 2009 | 1 | 2009 |
| HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning Y Shin, I Shin, D Baek, D Kim, S Paik IEEE Transactions on Circuits and Systems I: Regular Papers 61 (1), 146-159, 2013 | | 2013 |
| Introducing irregularity to routing architecture of structured ASIC for better routability I Shin, D Baek, Y Shin 2012 International Conference on Field-Programmable Technology, 224-228, 2012 | | 2012 |
| Gate delay modeling for static timing analysis of body-biased circuits D Baek, I Shin, Y Shin 2012 IEEE International Conference on IC Design & Technology, 1-4, 2012 | | 2012 |
| Selectively patterned masks: Beyond structured ASIC D Baek, I Shin, S Paik, Y Shin 2010 International SoC Design Conference, 154-157, 2010 | | 2010 |
Youngsoo ShinProfessor of Electrical Engineering, KAISTVerified email at ee.kaist.ac.kr
