Andreas Veneris
Andreas Veneris
Connaught Scholar and Professor of Electrical and Computer Engineering, cross-appointed with
Verified email at eecg.toronto.edu - Homepage
Title
Cited by
Cited by
Year
Fault diagnosis and logic debugging using Boolean satisfiability
A Smith, A Veneris, MF Ali, A Viglas
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
3232005
Improved design debugging using maximum satisfiability
S Safarpour, H Mangassarian, A Veneris, MH Liffiton, KA Sakallah
Formal Methods in Computer Aided Design (FMCAD'07), 13-19, 2007
1352007
Design error diagnosis and correction via test vector simulation
A Veneris, IN Hajj
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
1281999
Astraea: A decentralized blockchain oracle
J Adler, R Berryhill, A Veneris, Z Poulos, N Veira, A Kastania
2018 IEEE international conference on internet of things (IThings) and IEEE …, 2018
1052018
Automated design debugging with maximum satisfiability
Y Chen, S Safarpour, J Marques-Silva, A Veneris
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
1052010
Post-verification debugging of hierarchical designs
MF Ali, S Safarpour, A Veneris, MS Abadir, R Drechsler
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
1052005
Design diagnosis using Boolean satisfiability
A Smith, A Veneris, A Viglas
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004
902004
Debugging sequential circuits using Boolean satisfiability
MF Ali, A Veneris, S Safarpour, M Abadir, R Drechsler, A Smith
Fifth International Workshop on Microprocessor Test and Verification (MTV'04 …, 2004
822004
Incremental fault diagnosis
JB Liu, A Veneris
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
782005
Fault equivalence and diagnostic test generation using ATPG
A Veneris, R Chang, MS Abadir, M Amiri
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
732004
Efficient SAT-based Boolean matching for FPGA technology mapping
S Safarpour, A Veneris, G Baeckler, R Yuan
Proceedings of the 43rd Annual Design Automation Conference, 466-471, 2006
592006
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test
H Mangassarian, A Veneris, S Safarpour, M Benedetti, D Smith
2007 IEEE/ACM International Conference on Computer-Aided Design, 240-245, 2007
582007
Seamless integration of SER in rewiring-based design space exploration
S Almukhaizim, Y Makris, YS Yang, A Veneris
2006 IEEE International Test Conference, 1-9, 2006
542006
L-CBF: a low-power, fast counting Bloom filter architecture
E Safi, A Moshovos, A Veneris
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (6), 628-638, 2008
462008
Abstraction and refinement techniques in automated design debugging
S Safarpour, A Veneris
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
462007
Robust QBF encodings for sequential circuits with applications to verification, debug, and test
H Mangassarian, A Veneris, M Benedetti
IEEE Transactions on Computers 59 (7), 981-994, 2010
422010
Automating logic rectification by approximate SPFDs
YS Yang, S Sinha, A Veneris, RK Brayton
2007 Asia and South Pacific Design Automation Conference, 402-407, 2007
402007
Automated data analysis solutions to silicon debug
YS Yang, N Nicolici, A Veneris
2009 Design, Automation & Test in Europe Conference & Exhibition, 982-987, 2009
392009
Incremental diagnosis and correction of multiple faults and errors
A Veneris, JB Liu, M Amiri, MS Abadir
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
382002
Managing don't cares in Boolean satisfiability
S Safarpour, A Veneris, R Drechsler, J Lee
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
372004
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