Luis Lastras
Cited by
Cited by
Phase change memory technology
GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ...
Journal of Vacuum Science & Technology B, Nanotechnology and …, 2010
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MK Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
2009 42nd Annual IEEE/ACM international symposium on microarchitecture …, 2009
Improving read performance of phase change memories via write cancellation and write pausing
MK Qureshi, MM Franceschini, LA Lastras-Montano
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
Morphable memory system: a robust architecture for exploiting multi-level phase change memories
MK Qureshi, MM Franceschini, LA Lastras-Montano, JP Karidis
Proceedings of the 37th annual international symposium on Computer …, 2010
PreSET: Improving performance of phase change memories by exploiting asymmetry in write times
MK Qureshi, MM Franceschini, A Jagmohan, LA Lastras
ACM SIGARCH Computer Architecture News 40 (3), 380-391, 2012
Resistive memory devices having a not-and (NAND) structure
MJ Breitwisch, GS Ditlow, MM Franceschini, LA Lastras-Montano, ...
US Patent 8,107,276, 2012
Systems and methods for error detection in a memory system
LA Lastras-Montano
US Patent 7,949,931, 2011
High availability memory system
JA O'connor, KC Gower, LA Lastras-Montano, WE Maule
US Patent 8,086,783, 2011
Heterogeneous recovery in a redundant memory system
KC Gower, LA Lastras-Montano, PJ Meaney, VK Papazova, E Stephens
US Patent 8,775,858, 2014
Practical and secure pcm systems by online detection of malicious write streams
MK Qureshi, A Seznec, LA Lastras, MM Franceschini
2011 IEEE 17th International symposium on high performance computer …, 2011
System and method for providing a high fault tolerant memory system
LA Lastras-Montano, JA O'connor, LC Alves, WJ Clarke, TJ Dell, ...
US Patent 8,041,989, 2011
System and method for error correction and detection in a memory system
JA O'connor, LA Lastras-Montano, LC Alves, WJ Clarke, TJ Dell, ...
US Patent 8,041,990, 2011
Iterative write pausing techniques to improve read latency of memory systems
MM Franceschini, LA Lastras-Montano, MK Qureshi, V Srinivasan
US Patent 8,004,884, 2011
All sources are nearly successively refinable
L Lastras, T Berger
IEEE Transactions on Information Theory 47 (3), 918-926, 2001
Adaptive endurance coding of non-volatile memories
MM Franceschini, A Jagmohan, JP Karidis, LA Lastras-Montano
US Patent 8,341,501, 2012
Prediction based priority scheduling
DM Daly, PA Franaszek, LA Lastras-Montano
US Patent 8,185,899, 2012
Reliable memories with subline accesses
J Han, LA Lastras-Montano
2007 IEEE International Symposium on Information Theory, 2531-2535, 2007
System and method for providing DRAM device-level repair via address remappings external to the device
LA Lastras-Montano, DL Anand, JH Dreibelbis, CA Kilmer, WE Maule, ...
US Patent 7,984,329, 2011
Write amplification reduction in NAND flash through multi-write coding
A Jagmohan, M Franceschini, L Lastras
2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST), 1-6, 2010
On the redundancy of Slepian–Wolf coding
D He, LA Lastras-Montaņo, E Yang, A Jagmohan, J Chen
IEEE transactions on information theory 55 (12), 5607-5627, 2009
The system can't perform the operation now. Try again later.
Articles 1–20