Qiuling Zhu
Qiuling Zhu
Verified email at andrew.cmu.edu
Cited by
Cited by
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing
Q Zhu, B Akin, HE Sumbul, F Sadi, JC Hoe, L Pileggi, F Franchetti
2013 IEEE international 3D systems integration conference (3DIC), 1-7, 2013
Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware
Q Zhu, T Graf, HE Sumbul, L Pileggi, F Franchetti
2013 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2013
Efficient and secure intellectual property (IP) design with split fabrication
K Vaidyanathan, R Liu, E Sumbul, Q Zhu, F Franchetti, L Pileggi
2014 IEEE international symposium on hardware-oriented security and trust …, 2014
Line buffer unit for image processor
N Desai, A Meixner, Q Zhu, JR Redgrave, O Shacham, DF Finchelstein
US Patent 9,756,268, 2017
Virtual linebuffers for image signal processors
Q Zhu, O Shacham, JR Redgrave, DF Finchelstein, A Meixner
US Patent 9,749,548, 2017
Synergistic combinations of phenolic antioxidants
H Koch, A Lichtblau, M Zäh, C Kröhnke
US Patent 6,646,035, 2003
Method and device for patient temperature control employing optimized rewarming
M Magers
US Patent 6,830,581, 2004
Design automation framework for application-specific logic-in-memory blocks
Q Zhu, K Vaidyanathan, O Shacham, M Horowitz, L Pileggi, F Franchetti
2012 IEEE 23rd International Conference on Application-Specific Systems …, 2012
Architecture for high performance, power efficient, programmable image processing
Q Zhu, O Shacham, A Meixner, JR Redgrave, DF Finchelstein, ...
US Patent 9,965,824, 2018
Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
A Meixner, O Shacham, D Patterson, DF Finchelstein, Q Zhu, ...
US Patent 10,095,479, 2018
Two dimensional shift array for image processor
O Shacham, JR Redgrave, A Meixner, Q Zhu, DF Finchelstein, ...
US Patent 9,769,356, 2017
Sheet generator for image processor
A Meixner, JR Redgrave, O Shacham, Q Zhu, DF Finchelstein
US Patent 10,291,813, 2019
Energy efficient processor core architecture for image processor
A Meixner, JR Redgrave, O Shacham, DF Finchelstein, Q Zhu
US Patent 9,772,852, 2017
Method for determining biological agents in living target cells
M Vega
US Patent App. 10/275,253, 2003
3DIC memory chips including computational logic-in-memory for performing accelerated data processing
F Franchetti, Q Zhu, LT Pileggi
US Patent 9,286,216, 2016
Burial structure for the interment of human remains and significant memorabilia
DT Dudek, PR Heard
US Patent 6,799,399, 2004
Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip
K Vaidyanathan, Q Zhu, L Liebmann, K Lai, S Wu, R Liu, Y Liu, A Strojwas, ...
Journal of Micro/Nanolithography, MEMS, and MOEMS 14 (1), 011007, 2014
Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory
Q Zhu, CR Berger, EL Turner, L Pileggi, F Franchetti
2012 IEEE International Conference on Acoustics, Speech and Signal …, 2012
Application-specific logic-in-memory for polar format synthetic aperture radar
Q Zhu, EL Turnerz, CR Bergery, L Pileggi, F Franchetti
Proc. High Performance Embedded Computing (HPEC), 2011
A robust radio frequency identification system enhanced with spread spectrum technique
Z Qiuling, Z Chun, L Zhongqi, W Jingchao, L Fule, W Zhihua
2009 IEEE International Symposium on Circuits and Systems, 37-40, 2009
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