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Agustín Navarro Torres
Agustín Navarro Torres
Postdoctoral Researcher, Universidad de Murcia
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Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP
A Navarro-Torres, J Alastruey-Benedé, P Ibáñez-Marín, V Viñals-Yúfera
Plos one 14 (8), e0220135, 2019
352019
Berti: an accurate local-delta data prefetcher
A Navarro-Torres, B Panda, J Alastruey-Benedé, P Ibáñez, ...
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 975-991, 2022
192022
Exposing abstraction-level interactions with a parallel ray tracer
A Valero, DS Gracia, RG Tejero, LM Ramos, A Navarro-Torres, A Muñoz, ...
Proceedings of the Workshop on Computer Architecture Education, 1-8, 2019
22019
BALANCER: bandwidth allocation and cache partitioning for multicore processors
A Navarro-Torres, J Alastruey-Benedé, P Ibáñez, V Viñals-Yúfera
The Journal of Supercomputing 79 (9), 10252-10276, 2023
12023
Synchronization strategies on many-core smt systems
A Navarro-Torres, J Alastruey-Benedé, P Ibáñez-Marín, M Carpen-Amarie
2021 IEEE 33rd International Symposium on Computer Architecture and High …, 2021
12021
Correction: Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP
A Navarro-Torres, J Alastruey-Benedé, P Ibáñez-Marín, V Viñals-Yúfera
Plos one 19 (5), e0303712, 2024
2024
Contributions to high performance memory hierarchies: program characterization, resoruce control, transactional synchronization and hardware perfetching
A Navarro Torres, J Alastruey Benedé, PE Ibáñez Marín
Memory Hierarchy Performance Characterization of SPEC CPU2017
A Navarro-Torres, P Ibáñez-Marín, J Alastruey-Benedé, V Viñals-Yúfera
Caracterización en memoria de la suite de Benchmarks SPEC CPU2017
A Navarro Torres, PE Ibáñez Marín
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Articles 1–9