Gerald Sobelman
Gerald Sobelman
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Cited by
Cited by
CMOS circuit design of threshold gates with hysteresis
GE Sobelman, K Fant
1998 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 61-64, 1998
Architectures for multi-gigabit wire-linked clock and data recovery
M Hsieh, GE Sobelman
IEEE Circuits and systems magazine 8 (4), 45-57, 2008
Hardware efficient mixed radix-25/16/9 FFT for LTE systems
J Chen, J Hu, S Lee, GE Sobelman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 221-229, 2014
Improved vlsi designs for multiplication and inversion in gf (2/sup m/) over normal bases
L Gao, GE Sobelman
Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No …, 2000
Elliptic curve scalar multiplier design using FPGAs
L Gao, S Shrivastava, GE Sobelman
International Workshop on Cryptographic Hardware and Embedded Systems, 257-268, 1999
A reduced-complexity architecture for LDPC layered decoding schemes
S Kim, GE Sobelman, H Lee
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (6 …, 2010
Low-power multiplier design using delayed evaluation
GE Sobelman, DL Raatz
1995 IEEE International Symposium on Circuits and Systems (ISCAS) 3, 1564-1567, 1995
CDMA-based network-on-chip architecture
D Kim, M Kim, GE Sobelman
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004 …, 2004
A new low-voltage full adder circuit
H Lee, GE Sobelman
Proceedings Great Lakes Symposium on VLSI, 88-92, 1997
New low-voltage circuits for XOR and XNOR
H Lee, GE Sobelman
Proceedings IEEE SOUTHEASTCON'97.'Engineering the New Century', 225-229, 1997
New XOR/XNOR and full adder circuits for low voltage, low power applications
H Lee, GE Sobelman
Microelectronics Journal 29 (8), 509-517, 1998
FPGA-based FIR filters using digit-serial arithmetic
H Lee, GE Sobelman
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit …, 1997
Network-on-chip link analysis under power and performance constraints
M Kim, D Kim, GE Sobelman
2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp., 2006
Performance evaluation and optimal design for FPGA-based digit-serial DSP functions
H Lee, GE Sobelman
Computers & Electrical Engineering 29 (2), 357-377, 2003
Comparison of LC and Ring VCOs for PLLs in a 90 nm Digital CMOS Process
M Hsieh, GE Sobelman
대한전자공학회 ISOCC, 19-22, 2006
A compact fast variable key size elliptic curve cryptosystem coprocessor
L Gao, H Lee, GE Sobelman
Seventh Annual IEEE Symposium on Field-Programmable Custom Computing …, 1999
Mesh-star hybrid NoC architecture with CDMA switch
W Lee, GE Sobelman
2009 IEEE International Symposium on Circuits and Systems (ISCAS), 1349-1352, 2009
MPEG-4 performance analysis for a CDMA network-on-chip
M Kim, D Kim, GE Sobelman
Proceedings. 2005 International Conference on Communications, Circuits and …, 2005
Time borrowing in high-speed functional units using skew-tolerant domino circuits
G Jung, V Perepelitsa, GE Sobelman
2000 IEEE International Symposium on Circuits and Systems (ISCAS) 5, 641-644, 2000
Digital signal processor with delayed-evaluation array multipliers and low-power memory addressing
DL Raatz, GE Sobelman
US Patent 5,333,119, 1994
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