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Satrajit Chatterjee
Satrajit Chatterjee
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Title
Cited by
Cited by
Year
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
A Mishchenko, S Chatterjee, R Brayton
Proceedings of the 43rd annual Design Automation Conference, 532-535, 2006
6382006
Improvements to technology mapping for LUT-based FPGAs
A Mishchenko, S Chatterjee, R Brayton
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field …, 2006
2472006
Improvements to combinational equivalence checking
A Mishchenko, S Chatterjee, R Brayton, N Een
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
2252006
Combinational and sequential mapping with priority cuts
A Mishchenko, S Cho, S Chatterjee, R Brayton
2007 IEEE/ACM International Conference on Computer-Aided Design, 354-361, 2007
2232007
FRAIGs: A unifying representation for logic synthesis and verification
A Mishchenko, S Chatterjee, R Jiang, RK Brayton
ERL Technical Report, 2005
2012005
Reducing structural bias in technology mapping
S Chatterjee, A Mishchenko, RK Brayton, X Wang, T Kam
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1972006
Learning and memorization
S Chatterjee
International conference on machine learning, 755-763, 2018
712018
Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics
S Chatterjee, M Kishinevsky
Formal Methods in System Design 40, 147-169, 2012
672012
Boolean factoring and decomposition of logic networks
A Mishchenko, R Brayton, S Chatterjee
2008 IEEE/ACM International Conference on Computer-Aided Design, 38-44, 2008
632008
xMAS: Quick formal modeling of communication fabrics to enable verification
S Chatterjee, M Kishinevsky, UY Ogras
IEEE Design & Test of Computers 29 (3), 80-88, 2012
612012
Verifying deadlock-freedom of communication fabrics
A Gotmanov, S Chatterjee, M Kishinevsky
Verification, Model Checking, and Abstract Interpretation: 12th …, 2011
572011
Coherent gradients: An approach to understanding generalization in gradient descent-based optimization
S Chatterjee
arXiv preprint arXiv:2002.10657, 2020
562020
Factor cuts
S Chatterjee, A Mishchenko, R Brayton
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
532006
Quick formal modeling of communication fabrics to enable verification
S Chatterjee, M Kishinevsky, UY Ogras
2010 IEEE International High Level Design Validation and Test Workshop …, 2010
462010
Logic synthesis meets machine learning: Trading exactness for generalization
S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ...
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
382021
Integrating logic synthesis, technology mapping, and retiming
A Mishchenko, S Chatterjee, R Brayton, P Pan
Proc. IWLS'05, 383-390, 2006
342006
On the generalization mystery in deep learning
S Chatterjee, P Zielinski
arXiv preprint arXiv:2203.10036, 2022
332022
Technology mapping with Boolean matching, supergates and choices
A Mishchenko, S Chatterjee, R Brayton, X Wang, T Kam
Berkeley Logic Synthesis and Verification Group, 2005
312005
Enabling binary neural network training on the edge
E Wang, JJ Davis, D Moro, P Zielinski, JJ Lim, C Coelho, S Chatterjee, ...
Proceedings of the 5th international workshop on embedded and mobile deep …, 2021
292021
Apollo: Transferable architecture exploration
A Yazdanbakhsh, C Angermueller, B Akin, Y Zhou, A Jones, M Hashemi, ...
arXiv preprint arXiv:2102.01723, 2021
272021
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