Giuseppe Di Guglielmo
Giuseppe Di Guglielmo
Associate Research Scientist, Columbia University
Verified email at - Homepage
Cited by
Cited by
An analysis of accelerator coupling in heterogeneous architectures
EG Cota, P Mantovani, G Di Guglielmo, LP Carloni
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
HIFSuite: Tools for HDL code conversion and manipulation
N Bombieri, G Di Guglielmo, M Ferrari, F Fummi, G Pravadelli, F Stefanni, ...
EURASIP Journal on Embedded Systems 2010, 1-20, 2010
Efficient generation of stimuli for functional verification by backjumping across extended FSMs
G Di Guglielmo, L Di Guglielmo, F Fummi, G Pravadelli
Journal of Electronic Testing 27 (2), 137-162, 2011
COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators
L Piccolboni, P Mantovani, GD Guglielmo, LP Carloni
ACM Transactions on Embedded Computing Systems (TECS) 16 (5s), 1-22, 2017
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems
P Mantovani, EG Cota, K Tien, C Pilato, G Di Guglielmo, K Shepard, ...
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
High-level synthesis of accelerators in embedded scalable platforms
P Mantovani, G Di Guglielmo, LP Carloni
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 204-211, 2016
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip
P Mantovani, EG Cota, C Pilato, G Di Guglielmo, LP Carloni
Proceedings of the International Conference on Compilers, Architectures and …, 2016
Semi-formal functional verification by EFSM traversing via NuSMV
G Di Guglielmo, F Fummi, G Pravadelli, S Soffia, M Roveri
2010 IEEE international High level design validation and test workshop …, 2010
RTOS-aware refinement for TLM2. 0-based HW/SW designs
M Becker, G Di Guglielmo, F Fummi, W Mueller, G Pravadelli, T Xie
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
System-level optimization of accelerator local memory for heterogeneous systems-on-chip
C Pilato, P Mantovani, G Di Guglielmo, LP Carloni
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
EFSM manipulation to increase high-level ATPG effectiveness
G Di Guglielmo, F Fummi, C Marconcini, G Pravadelli
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-62, 2006
Compressing deep neural networks on FPGAs to binary and ternary precision with hls4ml
J Ngadiuba, V Loncar, M Pierini, S Summers, G Di Guglielmo, J Duarte, ...
Machine Learning: Science and Technology 2 (1), 015001, 2020
Dynamic property mining for embedded software
M Bonato, G Di Guglielmo, M Fujita, F Fummi, G Pravadelli
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2012
Fast inference of Boosted Decision Trees in FPGAs for particle physics
S Summers, G Di Guglielmo, J Duarte, P Harris, D Hoang, S Jindariani, ...
Journal of Instrumentation 15 (05), P05026, 2020
Automatic generation of compact formal properties for effective error detection
M Bertasi, G Di Guglielmo, G Pravadelli
2013 International Conference on Hardware/Software Codesign and System …, 2013
On the integration of model-driven design and dynamic assertion-based verification for embedded software
G Di Guglielmo, L Di Guglielmo, A Foltinek, M Fujita, F Fummi, ...
Journal of Systems and Software 86 (8), 2013
System-level memory optimization for high-level synthesis of component-based SoCs
C Pilato, P Mantovani, G Di Guglielmo, LP Carloni
Proceedings of the 2014 International Conference on Hardware/Software …, 2014
Design and implementation of a dynamic information flow tracking architecture to secure a RISC-V core for IoT applications
C Palmiero, G Di Guglielmo, L Lavagno, LP Carloni
2018 IEEE High Performance extreme Computing Conference (HPEC), 1-7, 2018
A design methodology for compositional high-level synthesis of communication-centric SoCs
G Di Guglielmo, C Pilato, LP Carloni
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
Combining dynamic slicing and mutation operators for ESL correction
U Repinski, H Hantson, M Jenihhin, J Raik, R Ubar, G Di Guglielmo, ...
2012 17th IEEE European Test Symposium (ETS), 1-6, 2012
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