| Transient-fault recovery for chip multiprocessors M Gomaa, C Scarbrough, TN Vijaykumar, I Pomeranz ACM SIGARCH Computer Architecture News 31 (2), 98-109, 2003 | 493 | 2003 |
| COMPACTEST: A method to generate compact test sets for combinational circuits I Pomeranz, LN Reddy, SM Reddy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 460 | 1993 |
| Transient-fault recovery using simultaneous multithreading TN Vijaykumar, I Pomeranz, K Cheng ACM SIGARCH Computer Architecture News 30 (2), 87-98, 2002 | 450 | 2002 |
| Techniques for minimizing power dissipation in scan and combinational circuits during test application V Dabholkar, S Chakravarty, I Pomeranz, S Reddy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998 | 377 | 1998 |
| Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits S Kajihara, I Pomeranz, K Kinoshita, SM Reddy Proceedings of the 30th International Design Automation Conference, 102-106, 1993 | 337 | 1993 |
| Preferred fill: A scalable method to reduce capture power for scan based designs S Remersaro, X Lin, Z Zhang, SM Reddy, I Pomeranz, J Rajski 2006 IEEE International Test Conference, 1-10, 2006 | 297 | 2006 |
| 3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits I Pomeranz, SM Reddy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993 | 197 | 1993 |
| On the generation of small dictionaries for fault location I Pomeranz, SM Reddy 1992 IEEE/ACM International Conference on Computer-Aided Design, 272-279, 1992 | 156 | 1992 |
| On n-detection test sets and variable n-detection test sets for transition faults I Pomeranz, SM Reddy IEEE transactions on computer-aided design of integrated circuits and …, 2000 | 155 | 2000 |
| On static compaction of test sequences for synchronous sequential circuits I Pomeranz, SM Reddy Proceedings of the 33rd annual Design Automation Conference, 215-220, 1996 | 152 | 1996 |
| On test data volume reduction for multiple scan chain designs SM Reddy, K Miyase, S Kajihara, I Pomeranz ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003 | 146 | 2003 |
| SOC test scheduling using simulated annealing W Zou, SM Reddy, I Pomeranz, Y Huang Proceedings. 21st VLSI Test Symposium, 2003., 325-330, 2003 | 144 | 2003 |
| Vector restoration based static compaction of test sequences for synchronous sequential circuits I Pomeranz, SM Reddy Proceedings International Conference on Computer Design VLSI in Computers …, 1997 | 134 | 1997 |
| Fault dictionary compression and equivalence class computation for sequential circuits PG Ryan, WK Fuchs, I Pomeranz Proceedings of 1993 International Conference on Computer Aided Design (ICCAD …, 1993 | 124 | 1993 |
| A low power pseudo-random BIST technique NZ Basturkmen, SM Reddy, I Pomeranz Journal of electronic testing 19, 637-644, 2003 | 119 | 2003 |
| On-chip compression of output responses with unknown values using LFSR reseeding M Naruse, I Pomeranz, SM Reddy, S Kundu International Test Conference, 2003. Proceedings. ITC 2003., 1060-1060, 2003 | 112 | 2003 |
| Classification of faults in synchronous sequential circuits I Pomeranz, SM Reddy IEEE Transactions on Computers 42 (9), 1066-1077, 1993 | 111 | 1993 |
| On the generation of scan-based test sets with reachable states for testing under functional operation conditions I Pomeranz Proceedings of the 41st annual Design Automation Conference, 928-933, 2004 | 110 | 2004 |
| On generating pseudo-functional delay fault tests for scan designs Z Zhang, SM Reddy, I Pomeranz 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 109 | 2005 |
| On reducing peak current and power during test W Li, SM Reddy, I Pomeranz IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design …, 2005 | 109 | 2005 |
