| Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs F Hapke, R Krenz-Baath, A Glowatz, J Schlöffel, H Hashempour, ... 2009 International Test Conference, 1-10, 2009 | 123 | 2009 |
| Defect-oriented cell-internal testing F Hapke, W Redemund, J Schloeffel, R Krenz-Baath, A Glowatz, M Wittke, ... 2010 IEEE International Test Conference, 1-10, 2010 | 66 | 2010 |
| A suite of IEEE 1687 benchmark networks A Tšertov, A Jutman, S Devadze, MS Reorda, E Larsson, FG Zadegan, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 53 | 2016 |
| Design, verification, and application of IEEE 1687 FG Zadegan, E Larsson, A Jutman, S Devadze, R Krenz-Baath 2014 IEEE 23rd Asian Test Symposium, 93-100, 2014 | 33 | 2014 |
| A new SAT-based ATPG for generating highly compacted test sets S Eggersglüß, R Krenz-Bååth, A Glowatz, F Hapke, R Drechsler 2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012 | 33 | 2012 |
| Access time minimization in IEEE 1687 networks R Krenz-Baath, FG Zadegan, E Larsson 2015 IEEE International Test Conference (ITC), 1-10, 2015 | 32 | 2015 |
| Cell-aware fault model creation and pattern generation F Hapke, R Krenz-Baath, A Glowatz, J Schloeffel, P Weseloh, M Wittke, ... US Patent App. 12/718,799, 2010 | 28 | 2010 |
| On optimization-based ATPG and its application for highly compacted test sets S Eggersglüß, K Schmitz, R Krenz-Bååth, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 27 | 2016 |
| Optimization-based multiple target test generation for highly compacted test sets S Eggersglüb, K Schmitz, R Krenz-Bååth, R Drechsler 2014 19th IEEE European Test Symposium (ETS), 1-6, 2014 | 23 | 2014 |
| Computing optimal communication schedules for time-triggered networks using an SMT solver C Schöler, R Krenz-Bååth, A Murshed, R Obermaisser 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), 1-9, 2016 | 18 | 2016 |
| Industrial application of IEEE P1687 for an automotive product M Keim, T Waayers, R Morren, F Hapke, R Krenz-Baath 2013 Euromicro Conference on Digital System Design, 453-461, 2013 | 18 | 2013 |
| Improved Boolean function hashing based on multiple-vertex dominators R Krenz, E Dubrova Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 17 | 2005 |
| Design and analysis of a self-timed duplex communication system A Yakovlev, S Furber, R Krenz, A Bystrov IEEE Transactions on Computers 53 (7), 798-814, 2004 | 16 | 2004 |
| Multi-targeting boolean satisfiability-based test pattern generation R Krenz-Baath, A Glowatz, F Hapke US Patent 8,689,069, 2014 | 14 | 2014 |
| Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs D Tille, S Eggersglüß, R Krenz-Bååth, J Schloeffel, R Drechsler 2010 15th IEEE European Test Symposium, 176-181, 2010 | 12 | 2010 |
| Fast algorithm for computing spectral transforms of Boolean and multiple-valued functions on circuit representation R Krenz, E Dubrova, A Kuehlmann 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings …, 2003 | 12 | 2003 |
| Optimal SAT-based scheduler for time-triggered networks-on-a-chip C Schöler, R Krenz-Bååth, A Murshed, R Obermaisser 10th IEEE International Symposium on Industrial Embedded Systems (SIES), 1-6, 2015 | 9 | 2015 |
| Upper-bound computation for optimal retargeting in IEEE1687 networks FG Zadegan, R Krenz-Baath, E Larsson 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 8 | 2016 |
| Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions. R Krenz, E Dubrova, A Kuehlmann IWLS, 321-326, 2002 | 7 | 2002 |
| On-chip logic to log failures during production testing and enable debugging for failure diagnosis F Hapke, J Schloeffel, M Wittke, R Krenz-Baath US Patent 8,423,845, 2013 | 5 | 2013 |
Erik LarssonLunds UniversitetVerified email at eit.lth.se
