Endri Bezati
Endri Bezati
Verified email at epfl.ch
Title
Cited by
Cited by
Year
Methods to explore design space for MPEG RMC codec specifications
S Casale-Brunet, A Elguindy, E Bezati, R Thavot, G Roquier, M Mattavelli, ...
Signal Processing: Image Communication 28 (10), 1278-1294, 2013
522013
High-level synthesis of dataflow programs for signal processing systems
E Bezati, M Mattavelli, JW Janneck
2013 8th International Symposium on Image and Signal Processing and Analysis†…, 2013
352013
High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms
E Bezati, R Thavot, G Roquier, M Mattavelli
Journal of real-time image processing 9 (1), 251-262, 2014
332014
High-level synthesis of dataflow programs for heterogeneous platforms: design flow tools and design space exploration
E Bezati
EPFL, Switzerland, 2015
30*2015
Synthesis and optimization of high-level stream programs
E Bezati, SC Brunet, M Mattavelli, JW Janneck
Proceedings of the 2013 Electronic System Level Synthesis Conference (ESLsyn†…, 2013
302013
Rvc-cal dataflow implementations of mpeg avc/h. 264 cabac decoding
E Bezati, M Mattavelli, M Raulet
2010 Conference on Design and Architectures for Signal and Image Processing†…, 2010
242010
Partitioning and optimization of high level stream applications for multi clock domain architectures
SC Brunet, E Bezati, C Alberti, M Mattavelli, E Amaldi, JW Janneck
SiPS 2013 Proceedings, 177-182, 2013
232013
Automated design flow for multi-functional dataflow-based platforms
C Sau, P Meloni, L Raffo, F Palumbo, E Bezati, S Casale-Brunet, ...
Journal of Signal Processing Systems 85 (1), 143-165, 2016
212016
Hardware and software synthesis of heterogeneous systems from dataflow programs
G Roquier, E Bezati, M Mattavelli
Journal of Electrical and Computer Engineering 2012, 2012
212012
A unified hardware/software co-synthesis solution for signal processing systems
E Bezati, H Yviquel, M Raulet, M Mattavelli
Proceedings of the 2011 Conference on Design & Architectures for Signal†…, 2011
212011
Coarse grain clock gating of streaming applications in programmable logic implementations
E Bezati, SC Brunet, M Mattavelli, JW Janneck
Proceedings of the 2014 electronic system level synthesis conference (ESLsyn†…, 2014
202014
Clock-gating of streaming applications for energy efficient implementations on FPGAs
E Bezati, S Casale-Brunet, M Mattavelli, JW Janneck
IEEE Transactions on Computer-Aided Design of Integrated Circuits and†…, 2016
192016
Synthesis and optimization of pipelines for HW implementations of dataflow programs
A Prihozhy, E Bezati, AAH Ab Rahman, M Mattavelli
IEEE Transactions on Computer-Aided Design of Integrated Circuits and†…, 2015
192015
Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program
AAH Ab Rahman, R Thavot, SC Brunet, E Bezati, M Mattavelli
Proceedings of the 2012 Conference on Design and Architectures for Signal†…, 2012
192012
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
C Sau, L Raffo, F Palumbo, E Bezati, S Casale-Brunet, M Mattavelli
2014 International Conference on Embedded Computer Systems: Architectures†…, 2014
142014
Efficient scheduling policies for dynamic data flow programs executed on multi-core
M Michalska, N Zufferey, J Boutellier, E Bezati, M Mattavelli
11th international meeting on logistics research, 2016
122016
Dataflow programs analysis and optimization using model predictive control techniques
M Canale, S Casale-Brunet, E Bezati, M Mattavelli, J Janneck
Journal of Signal Processing Systems 84 (3), 371-381, 2016
92016
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms
E Bezati, S Casale-Brunet, M Mattavelli, JW Janneck
2016 International conference on embedded computer systems: Architectures†…, 2016
92016
TURNUS: An open-source design space exploration framework for dynamic stream programs
S Casale-Brunet, M Wiszniewska, E Bezati, M Mattavelli, JW Janneck, ...
Proceedings of the 2014 Conference on Design and Architectures for Signal†…, 2014
92014
High-precision performance estimation for the design space exploration of dynamic dataflow programs
M Michalska, S Casale-Brunet, E Bezati, M Mattavelli
IEEE Transactions on Multi-Scale Computing Systems 4 (2), 127-140, 2017
82017
The system can't perform the operation now. Try again later.
Articles 1–20