| Explicit formulas for lattice wave digital filters L Gazsi IEEE Transactions on Circuits and Systems 32 (1), 68-88, 1985 | 358 | 1985 |
| A new network processor architecture for high-speed communications X Nie, L Gazsi, F Engel, G Fettweis 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and …, 1999 | 100 | 1999 |
| A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS N Da Dalt, E Thaller, P Gregorius, L Gazsi IEEE Journal of Solid-State Circuits 40 (7), 1482-1490, 2005 | 99 | 2005 |
| Parallel multithread processor (PMT) with split contexts L Gazsi, J Lin, S Mehrgardt, X Nie US Patent 7,526,636, 2009 | 91 | 2009 |
| Analog to digital conversion using irregular sampling A Wiesbauer, L Gazsi US Patent 7,746,256, 2010 | 45 | 2010 |
| Analog/digital converter configuration with sigma-delta modulators L Gazsi US Patent 5,075,679, 1991 | 36 | 1991 |
| Heterogeneous parallel multithread processor (HPMT) with local context memory sets for respective processor type groups and global context memory L Gazsi, J Lin, S Mehrgardt, X Nie US Patent 7,263,604, 2007 | 31 | 2007 |
| High-speed router L Gazsi, X Nie US Patent 7,079,538, 2006 | 25 | 2006 |
| A new design method for polyphase filters using all-pass sections W Drews, L Gazsi IEEE transactions on circuits and systems 33 (3), 346-348, 1986 | 21 | 1986 |
| Method of reconstructing data transmitted over a transmission path in a receiver and corresponding device L Gazsi, P Gregorius US Patent 7,095,803, 2006 | 19 | 2006 |
| A low jitter triple-band digital LC PLL in 130nm CMOS N Da Dalt, E Thaller, P Gregorius, L Gazsi Proceedings of the 30th European Solid-State Circuits Conference, 371-374, 2004 | 17 | 2004 |
| Digital phase locked loop for sub-μ technologies L Gazsi US Patent 7,573,955, 2009 | 16 | 2009 |
| Discrete optimization of coefficients in CSD code L Gazsi, SN Güllüoglu Proc. IEEE Mediterranean Electrotechnical Conf 2, c3, 08-09, 1983 | 16 | 1983 |
| Method for filtering a digital value train with improved noise behavior, and circuit configuration for performing the method F Leeb, L Gazsi US Patent 5,629,881, 1997 | 14 | 1997 |
| Two-wire/four-wire converter L Gazsi US Patent 5,175,763, 1992 | 14 | 1992 |
| Single chip filter bank with wave digital filters L Gazsi IEEE Transactions on Acoustics, Speech, and Signal Processing 30 (5), 709-718, 1982 | 13 | 1982 |
| Two-wire/four-wire converter L Gazsi US Patent 5,172,411, 1992 | 12 | 1992 |
| Digital circuit for sampling rate variation and signal filtering and method for constructing the circuit L Gazsi US Patent 4,825,396, 1989 | 11 | 1989 |
| Adder-based digital signal processor architecture for 80 ns cycle time A Rainer, W Ulbrich, L Gazsi ICASSP'84. IEEE International Conference on Acoustics, Speech, and Signal …, 1984 | 11 | 1984 |
| Hardware implementation of wave digital filters using programmable digital signal processors L Gazsi Proc. Europ. Conf. Circuit Theory and Design, ECCTD'81, 1052-1057, 1981 | 10 | 1981 |
Nicola Da DaltAMDVerified email at amd.com
