| Split-cnn: Splitting window-based operations in convolutional neural networks for memory system optimization T Jin, S Hong Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 47 | 2019 |
| Residue cache: A low-energy low-area L2 cache architecture via compression and partial hits S Kim, J Lee, J Kim, S Hong Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 47 | 2011 |
| Ternary cache: Three-valued MLC STT-RAM caches S Hong, J Lee, S Kim 2014 IEEE 32nd International Conference on Computer Design (ICCD), 83-89, 2014 | 39 | 2014 |
| Attaché: Towards ideal memory compression by mitigating metadata bandwidth overheads S Hong, PJ Nair, B Abali, A Buyuktosunoglu, KH Kim, M Healy 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 37 | 2018 |
| Partial row activation for low-power dram system Y Lee, H Kim, S Hong, S Kim 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 31 | 2017 |
| Skinflint DRAM system: Minimizing DRAM chip writes for low power Y Lee, S Kim, S Hong, J Lee 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 28 | 2013 |
| Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling T Mahmood, S Kim, S Hong 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 26 | 2013 |
| Interpage-based endurance-enhancing lower state encoding for MLC and TLC flash memory storages W Lee, M Kang, S Hong, S Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (9 …, 2019 | 24 | 2019 |
| Touché: Towards ideal and efficient cache compression by mitigating tag area overheads S Hong, B Abali, A Buyuktosunoglu, MB Healy, PJ Nair Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 23 | 2019 |
| A case study of quantizing convolutional neural networks for fast disease diagnosis on portable medical devices M Garifulla, J Shin, C Kim, WH Kim, HJ Kim, J Kim, S Hong Sensors 22 (1), 219, 2021 | 22 | 2021 |
| Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU S Hong, S Kim 2010 IEEE International Conference on Computer Design, 342-349, 2010 | 22 | 2010 |
| A low-cost mechanism exploiting narrow-width values for tolerating hard faults in ALU S Hong, S Kim IEEE transactions on computers 64 (9), 2433-2446, 2014 | 12 | 2014 |
| TLB index-based tagging for cache energy reduction J Lee, S Hong, S Kim IEEE/ACM International Symposium on Low Power Electronics and Design, 85-90, 2011 | 11 | 2011 |
| TEPS: Transient error protection utilizing sub-word parallelism S Hong, S Kim 2009 IEEE Computer Society Annual Symposium on VLSI, 286-291, 2009 | 10 | 2009 |
| AVICA: An access-time variation insensitive L1 cache architecture S Hong, S Kim 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 65-70, 2013 | 9 | 2013 |
| Cramsim: Controller and memory simulator MB Healy, S Hong Proceedings of the International Symposium on Memory Systems, 83-85, 2017 | 8 | 2017 |
| Ensuring cache reliability and energy scaling at near-threshold voltage with macho T Mahmood, S Hong, S Kim IEEE Transactions on Computers 64 (6), 1694-1706, 2014 | 8 | 2014 |
| Cid: Co-architecting instruction cache and decompression system for embedded systems J Kim, S Hong, J Hong, S Kim IEEE Transactions on Computers 70 (7), 1132-1145, 2020 | 6 | 2020 |
| Adam: Adaptive block placement with metadata embedding for hybrid caches B Kim, PJ Nair, S Hong 2020 IEEE 38th International Conference on Computer Design (ICCD), 421-424, 2020 | 4 | 2020 |
| Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation O Kwon, Y Lee, S Hong IEEE Access 10, 114552-114565, 2022 | 3 | 2022 |
Prashant NairAssistant Professor, University of British ColumbiaVerified email at ece.ubc.ca
