High-throughput architecture for H. 264/AVC CABAC compression system RR Osorio, JD Bruguera IEEE Transactions on Circuits and Systems for Video Technology 16 (11), 1376 …, 2006 | 110 | 2006 |
Arithmetic coding architecture for H. 264/AVC CABAC compression system RR Osorio, JD Bruguera Euromicro Symposium on Digital System Design, 2004. DSD 2004., 62-69, 2004 | 81 | 2004 |
A new architecture for fast arithmetic coding in H. 264 advanced video coder RR Osorio, JD Bruguera 8th Euromicro Conference on Digital System Design (DSD'05), 298-305, 2005 | 38 | 2005 |
Improving scalability of application-level checkpoint-recovery by reducing checkpoint sizes I Cores, G Rodríguez, MJ Martín, P González, RR Osorio New Generation Computing 31, 163-185, 2013 | 33 | 2013 |
Truncated SIMD multiplier architecture for approximate computing in low-power programmable processors RR Osorio, G Rodriguez IEEE Access 7, 56353-56366, 2019 | 26 | 2019 |
A unified architecture for H. 264 multiple block-size DCT with fast and low cost quantization JD Bruguera, RR Osorio 9th EUROMICRO Conference on Digital System Design (DSD'06), 407-414, 2006 | 26 | 2006 |
Digit on-line large radix CORDIC rotator RR Osorio, E Antelo, JD Bruguera, J Villalba, EL Zapata Proceedings The International Conference on Application Specific Array …, 1995 | 19 | 1995 |
An efficient ant colony optimization framework for HPC environments P González, RR Osorio, XC Pardo, JR Banga, R Doallo Applied Soft Computing 114, 108058, 2022 | 18 | 2022 |
A VLSI implementation of an arithmetic coder for image compression M Peon, RR Osorio, JD Bruguera EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of …, 1997 | 15 | 1997 |
An FPGA architecture for CABAC decoding in manycore systems RR Osorio, JD Bruguera 2008 International Conference on Application-Specific Systems, Architectures …, 2008 | 13 | 2008 |
View-dependent, scalable texture streaming in 3-D QoS with MPEG-4 visual texture coding G Lafruit, E Delfosse, R Osorio, W Van Raemdonck, V Ferentinos, ... IEEE transactions on circuits and systems for video technology 14 (7), 1021-1031, 2004 | 13 | 2004 |
Method for syntactically analyzing a bit stream using a schema and a method of generating a bit stream based thereon R Osorio US Patent 7,570,180, 2009 | 12 | 2009 |
New arithmetic coder/decoder architectures based on pipelining RR Osorio, JD Bruguera Proceedings IEEE International Conference on Application-Specific Systems …, 1997 | 12 | 1997 |
Performance analysis of massively parallel embedded hardware architectures for retinal image processing A Nieto, V Brea, DL Vilariño, RR Osorio EURASIP Journal on Image and Video Processing 2011, 1-17, 2011 | 11 | 2011 |
A combined memory compression and hierarchical motion estimation architecture for video encoding in embedded systems RR Osorio, JD Bruguera 9th EUROMICRO Conference on Digital System Design (DSD'06), 269-274, 2006 | 9 | 2006 |
High-speed FPGA architecture for CABAC decoding acceleration in H. 264/AVC standard RR Osorio, JD Bruguera Journal of Signal Processing Systems 72 (2), 119-132, 2013 | 7 | 2013 |
High Performance Image Processing on a Massively Parallel Processor Array RR Osorio, C Diaz-Resco, JD Bruguera 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 7 | 2009 |
Architectures for arithmetic coding in image compression RR Osorio, JD Bruguera 2000 10th European Signal Processing Conference, 1-4, 2000 | 7 | 2000 |
Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model RR Osorio 2016 IEEE 27th International Conference on Application-specific Systems …, 2016 | 6 | 2016 |
A digital cellular-based system for retinal vessel-tree extraction CD Resco, A Nieto, RR Osorio, VM Brea, DL Vilarino 2009 European Conference on Circuit Theory and Design, 835-838, 2009 | 5 | 2009 |