| Optimization of quantum circuit mapping using gate transformation and commutation T Itoko, R Raymond, T Imamichi, A Matsuo Integration 70, 43-50, 2020 | 125 | 2020 |
| Quantum circuit compilers using gate commutation rules T Itoko, R Raymond, T Imamichi, A Matsuo, AW Cross Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 51 | 2019 |
| Changing the gate order for optimal LNN conversion A Matsuo, S Yamashita Reversible Computation: Third International Workshop, RC 2011, Gent, Belgium …, 2012 | 47 | 2012 |
| Reducing the overhead of mapping quantum circuits to IBM Q system A Matsuo, W Hattori, S Yamashita 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 34 | 2019 |
| Quantum machine learning on near-term quantum devices: Current state of supervised and unsupervised techniques for real-world applications Y Gujju, A Matsuo, R Raymond Physical Review Applied 21 (6), 067001, 2024 | 20 | 2024 |
| An efficient method for quantum circuit placement problem on a 2-D grid A Matsuo, S Yamashita Reversible Computation: 11th International Conference, RC 2019, Lausanne …, 2019 | 13 | 2019 |
| Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization Problems SY Atsushi Matsuo, Yudai Suzuki arXiv preprint arXiv:2006.05643, 2020 | 11 | 2020 |
| A SAT approach to the initial mapping problem in SWAP gate insertion for commuting gates A Matsuo, S Yamashita, DJ Egger IEICE Transactions on Fundamentals of Electronics, Communications and …, 2023 | 9 | 2023 |
| Automatic generation of Ising Hamiltonians for solving optimization problems in quantum computing A Matsuo, T Imamichi, M Pistoia US Patent 11,620,534, 2023 | 8 | 2023 |
| System and method for handling inequality constraints in mixed binary optimization on quantum computers S Woerner, DJ Egger, JR Glick, T Imamichi, A Matsuo US Patent 11,651,264, 2023 | 6 | 2023 |
| Enhancing VQE Convergence for Optimization Problems with Problem-Specific Parameterized Quantum Circuits A Matsuo, Y Suzuki, I Hamamura, S Yamashita IEICE TRANSACTIONS on Information and Systems 106 (11), 1772-1782, 2023 | 5 | 2023 |
| Mapping logical qubits on a quantum circuit T Itoko, A Matsuo US Patent 11,010,518, 2021 | 3 | 2021 |
| An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement A Matsuo, W Hattori, S Yamashita IEICE Transactions on Fundamentals of Electronics, Communications and …, 2023 | 2 | 2023 |
| Dynamical decomposition and mapping of mpmct gates to nearest neighbor architectures A Matsuo, W Hattori, S Yamashita Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 1 | 2021 |
| Optimization for Gaussian Elimination-based NNA-compliant Circuit Synthesis method by Inserting CNOT Gates Z Qi, A Matsuo, S Yamashita IEEE International Conference on Quantum Computing and Engineering, 2024 | | 2024 |
| Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-based Quantum Circuit Synthesis D CLARINO, N ASADA, A MATSUO, S YAMASHITA IEICE Transactions on Information and Systems, 2024 | | 2024 |
| Variational Quantum Eigensolver and Its Applications A Matsuo International Conference on Reversible Computation, 22-41, 2021 | | 2021 |
| Mapping logical qubits on a quantum circuit T Itoko, A Matsuo US Patent 10,657,304, 2020 | | 2020 |
| Fault-Tolerant Design with Less Overhead than DMR A Matsuo, S Yamashita IEICE Technical Report; IEICE Tech. Rep. 113 (320), 33-37, 2013 | | 2013 |
| Partially-Programmable Circuits with CAMs A Matsuo, S Yamashita, H Yoshida IEICE Technical Report; IEICE Tech. Rep. 112 (320), 31-36, 2012 | | 2012 |
