Dr. Vikas Maheshwari
Dr. Vikas Maheshwari
Professor, ECE Dept
Подтвержден адрес электронной почты в домене gniindia.org
Название
Процитировано
Процитировано
Год
Delay analysis for on-chip vlsi interconnect using gamma distribution function
R Kar, V Maheshwari, AK Mal, AK Bhattacharjee
International Journal of Computer Applications 975, 8887, 2010
102010
Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90nm process technology
A Gupta, V Maheshwari, S Sharma, R Kar
International Conference on Computing, Communication & Automation, 1215-1219, 2015
92015
An explicit crosstalk aware delay modelling for on-chip VLSI RLC interconnect with skin effect
V Maheshwari, S Lavania, D Sengupta, R Kar, D Mandal, ...
Journal of Electron Devices 10, 499-505, 2011
92011
Brain tumor detection by microwave imaging using planner antenna
H Gupta, V Maheshwari, VV Thakery
International Journal of Bio-Science and Bio-Technology 8 (5), 201-210, 2016
82016
Efficient coupled noise estimation for RLC on-chip interconnect
V Maheshwari, S Gupta, K Khare, V Yadav, R Kar, D Mandal, ...
2012 IEEE Symposium on Humanities, Science and Engineering Research, 1125-1129, 2012
72012
An explicit approach for delay evaluation for on-chip RC interconnects using beta distribution function by moment matching technique
R Kar, V Maheshwari, S Pathak, MSK Reddy, AK Mal, AK Bhattacharjee
2010 International Conference on Recent Trends in Information …, 2010
72010
Modeling of on-chip global RLCG interconnect delay for step input
R Kar, V Maheshwari, A Choudhary, A Singh
2010 International Conference on Computer and Communication Technology …, 2010
62010
Coupling aware explicit delay metric for on-chip rlc interconnect for ramp input
R Kar, V Maheshwari, A Choudhary, A Singh
International Journal of Signal & Image Processing (IJSIP) 1 (2), 14-19, 2010
62010
Area Optimization of CMOS Full Adder Design Using 3T XOR
S Malipatil, V Maheshwari, MB Chandra
2020 International Conference on Wireless Communications Signal Processing …, 2020
52020
Accurate estimation of on-chip global RLC interconnect delay for step input
R Kar, V Maheshwari, V Agarwal, A Choudhary, A Singh, AK Mai, ...
2010 International Conference on Computer and Communication Technology …, 2010
52010
Crosstalk aware bandwidth modeling for distributed on-chip RLCG interconnects using difference model approach
R Kar, V Maheshwari, M Maqbool, S Mondal, AK Mal, AK Bhattacharjee
2010 Second International conference on Computing, Communication and …, 2010
52010
Closed Form Expressions for Delay to Ramp Inputs for On-Chip VLSI RC Interconnect
V Maheshwari, P Sharma, A Goyal, VK Yadav, S Kumar
National Conference on Emerging Trends in Electrical, Instrumentation …, 0
5
Delay model for VLSI RLCG global interconnects line
V Maheshwari, A Baboo, B Kumar, R Kar, D Mandal, AK Bhattacharjee
2012 Asia Pacific Conference on Postgraduate Research in Microelectronics …, 2012
42012
Moment based delay modelling for on-chip RC global VLSI interconnect for unit ramp input
A Halder, V Maheshwari, A Goyal, R Kar, D Mandal, AK Bhattacharjee
2012 Ninth International Conference on Computer Science and Software …, 2012
42012
Analytical crosstalk modelling of on-chip RLC global interconnects with skin effect for ramp input
V Maheshwari, S Mukherjee, R Kar, D Mandal, AK Bhattacharjee
Procedia Technology 6, 814-821, 2012
42012
An accurate crosstalk noise estimation method for two simultaneously switched on-chip VLSI distributed RLCG global interconnects
R Kar, V Maheshwari, A Choudhary, A Singh, AK Mal, AK Bhattacharjee
2010 International Conference on Signal and Image Processing, 362-367, 2010
42010
An accurate delay metric for global on-chip vlsi rc interconnects using first three circuit moments
R Kar, V Maheshwari, MSK Reddy, V Agarwal, AK Mal, AK Bhattacharjee
14th VLSI Design And Test Symposium (VDAT 2010), July, 7-9, 2010
42010
Wave propagation based analytical delay and cross talk noise model for distributed on-chip RLCG interconnects
A Choudhary, V Maheshwari, A Singh, R Kar
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010 …, 2010
42010
Elmore's approximations based explicit delay and rise time model for distributed RLC on-chip VLSI global interconnect
V Maheshwari, S Agarwal, A Goyal, J Jain, S Kumar, R Kar, D Mandal, ...
2012 IEEE Symposium on Humanities, Science and Engineering Research, 1135-1139, 2012
32012
Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect
V Maheshwari, S Lavania, R Kar, D Mandal, AK Bhattacharjee
Journal of VLSI Design Tools & Technology 1 (1), 2011
32011
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