Valentina Salapura
Valentina Salapura
AMD Research
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Cited by
Cited by
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,081,501, 2015
Blue Gene: A vision for protein science using a petaflop supercomputer
F Allen, G Almasi, W Andreoni, D Beece, BJ Berne, A Bright, J Brunheroto, ...
IBM systems journal 40 (2), 310-327, 2001
The IBM Blue Gene/Q interconnection network and message unit
D Chen, NA Eisley, P Heidelberger, RM Senger, Y Sugawara, S Kumar, ...
Proceedings of 2011 International Conference for High Performance Computing …, 2011
Ultrascalable petaflop parallel supercomputer
MA Blumrich, D Chen, G Chiu, TM Cipolla, PW Coteus, AG Gara, ...
US Patent 7,761,687, 2010
Pipelined packet processing
RM Bunce, CJ Georgiou, V Salapura
US Patent 6,836,808, 2004
Sparkbench: a comprehensive benchmarking suite for in memory data analytic platform spark
M Li, J Tan, Y Wang, L Zhang, V Salapura
Proceedings of the 12th ACM international conference on computing frontiers, 1-8, 2015
Overview of the IBM Blue Gene/P project
G Almasi, S Asaad, RE Bellofatto, HR Bickford, MA Blumrich, B Brezzo, ...
IBM Journal of Research and Development 52 (1-2), 199-220, 2008
Single chip protocol converter
C Georgiou, V Gregurick, I Nair, V Salapura
US Patent App. 10/768,828, 2005
The ibm blue gene/q interconnection fabric
D Chen, N Eisley, P Heidelberger, R Senger, Y Sugawara, S Kumar, ...
IEEE Micro 32 (1), 32-43, 2011
Packet preprocessing interface for multiprocessor network handler
V Salapura, CJ Georgiou
US Patent 6,904,040, 2005
FPGA prototyping of a RISC processor core for embedded applications
M Gschwind, V Salapura, D Maurer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2), 241-250, 2001
Prefix computer instruction for compatibly extending instruction functionality
MK Gschwind, V Salapura
US Patent 9,311,093, 2016
Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
CJ Georgiou, VL Gregurick, I Nair, V Salapura
US Patent 7,412,588, 2008
Dynamic reallocation of data stored in buffers based on packet size
CJ Georgiou, V Salapura
US Patent 7,003,597, 2006
Low complexity speculative multithreading system based on unmodified microprocessor core
AG Gara, MK Gschwind, V Salapura
US Patent 7,404,041, 2008
Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
CJ Georgiou, VL Gregurick, V Salapura
US Patent 7,353,362, 2008
Quality of records containing service data
JA Bivens, V Salapura, M Vukovic
US Patent 8,478,624, 2013
Method and apparatus for software-assisted thermal management for electronic systems
MK Gschwind, V Salapura
US Patent 6,948,082, 2005
State recovery and lockstep execution restart in a system with multiprocessor pairing
A Gara, MK Gschwind, V Salapura
US Patent 8,635,492, 2014
Method and system of efficient packet reordering
CJ Georgiou, V Salapura
US Patent 7,477,644, 2009
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