| Semiconductor memory device K Nii, S Obayashi, H Makino, K Ishibashi, H Shinohara US Patent 7,502,275, 2009 | 232 | 2009 |
| Semiconductor storage device N Tsuda, K Nii US Patent 6,535,417, 2003 | 231 | 2003 |
| Semiconductor memory device capable of generating internal data read timing precisely Y Nakase, K Nii US Patent 6,760,269, 2004 | 221 | 2004 |
| Low-power embedded SRAM modules with expanded margins for writing M Yamaoka, N Maeda, Y Shinozaki, Y Shimazaki, K Nii, S Shimada, ... ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 211 | 2005 |
| A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits S Ohbayashi, M Yabuuchi, K Nii, Y Tsukamoto, S Imaoka, Y Oda, ... IEEE journal of solid-state circuits 42 (4), 820-829, 2007 | 195 | 2007 |
| An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment Y Morita, H Fujiwara, H Noguchi, Y Iguchi, K Nii, H Kawaguchi, ... 2007 IEEE Symposium on VLSI Circuits, 256-257, 2007 | 181 | 2007 |
| Semiconductor memory device K Nii, A Miyanishi US Patent 6,347,062, 2002 | 180 | 2002 |
| A low power SRAM using auto-backgate-controlled MT-CMOS K Nii, H Makino, Y Tujihashi, C Morishima, Y Hayakawa, H Nunogami, ... Proceedings. 1998 International Symposium on Low Power Electronics and …, 1998 | 166 | 1998 |
| A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment K Nii, M Yabuuchi, Y Tsukamoto, S Ohbayashi, Y Oda, K Usui, ... 2008 IEEE Symposium on VLSI Circuits, 212-213, 2008 | 152 | 2008 |
| Which is the best dual-port SRAM in 45-nm process technology?—8T, 10T single end, and 10T differential— H Noguchi, S Okumura, Y Iguchi, H Fujiwara, Y Morita, K Nii, ... 2008 IEEE International Conference on Integrated Circuit Design and …, 2008 | 143 | 2008 |
| A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications K Nii, Y Tsukamoto, T Yoshizawa, S Imaoka, Y Yamagami, T Suzuki, ... IEEE Journal of Solid-State Circuits 39 (4), 684-693, 2004 | 141 | 2004 |
| 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique M Yamaoka, N Maeda, Y Shinozaki, Y Shimazaki, K Nii, S Shimada, ... IEEE Journal of Solid-State Circuits 41 (3), 705-711, 2006 | 127 | 2006 |
| Semiconductor memory device with adjustable selected work line potential under low voltage condition K Nii, S Ohbayashi, Y Tsukamoto, M Yabuuchi US Patent 7,570,525, 2009 | 118 | 2009 |
| Semiconductor memory device with back gate potential control circuit for transistor in memory cell Y Tsukamoto, K Nii US Patent 7,079,413, 2006 | 117 | 2006 |
| Semiconductor integrated circuit device N Maeda, Y Shinozaki, M Yamaoka, Y Shimazaki, M Isoda, K Nii US Patent 7,113,421, 2006 | 108 | 2006 |
| A 45nm 0.6 V cross-point 8T SRAM with negative biased read/write assist M Yabuuchi, K Nii, Y Tsukamoto, S Ohbayashi, Y Nakase, H Shinohara 2009 Symposium on VLSI Circuits, 158-159, 2009 | 104 | 2009 |
| A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations K Nii, M Yabuuchi, Y Tsukamoto, S Ohbayashi, S Imaoka, H Makino, ... IEEE Journal of Solid-State Circuits 43 (1), 180-191, 2008 | 86 | 2008 |
| A 65 nm embedded sram with wafer level burn-in mode, leak-bit redundancy and cu e-trim fuse for known good die S Ohbayashi, M Yabuuchi, K Kono, Y Oda, S Imaoka, K Usui, T Yonezu, ... IEEE journal of solid-state circuits 43 (1), 96-108, 2008 | 86 | 2008 |
| A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations M Yabuuchi, K Nii, Y Tsukamoto, S Ohbayashi, S Imaoka, H Makino, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 86 | 2007 |
| A 250-MHz 18-Mb full ternary CAM with low-voltage matchline sensing scheme in 65-nm CMOS I Hayashi, T Amano, N Watanabe, Y Yano, Y Kuroda, M Shirata, K Dosaka, ... IEEE journal of solid-state circuits 48 (11), 2671-2680, 2013 | 76 | 2013 |
Hiroshi MakinoOsaka Institute of TechnologyVerified email at oit.ac.jp
