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Aliasger Zaidy
Aliasger Zaidy
Computer Architect, Deep Learning
Подтвержден адрес электронной почты в домене micron.com
Название
Процитировано
Процитировано
Год
Snowflake: An efficient hardware accelerator for convolutional neural networks
V Gokhale, A Zaidy, AXM Chang, E Culurciello
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
133*2017
Dynamic modeling and simulation of a PEM fuel cell: MATLAB and LabVIEW modeling approach
A Zaidy, P Pokharkar, R Krishnan, D Sonawane
2014 1st international conference on non conventional energy (ICONCE 2014 …, 2014
172014
Deep neural networks compiler for a trace-based accelerator (short WIP paper)
AXM Chang, A Zaidy, L Burzawa, E Culurciello
Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on …, 2018
14*2018
Low cost electricity meter reading system using GSM
AA Adhau, NM Patel, AT Zaidy, SL Patil, AS Deshpande
2013 International Conference on Energy Efficient Technologies for …, 2013
112013
Computation and memory bandwidth in deep neural networks
E Culurciello, A Zaidy, V Gokhale
Medium 5, 1-4, 2017
62017
Efficient compiler code generation for deep learning snowflake co-processor
AXM Chang, A Zaidy, E Culurciello
2018 1st Workshop on Energy Efficient Machine Learning and Cognitive …, 2018
42018
A high efficiency accelerator for deep neural networks
A Zaidy, AXM Chang, V Gokhale, E Culurciello
2018 1st Workshop on Energy Efficient Machine Learning and Cognitive …, 2018
32018
Compiler with an artificial neural network to optimize instructions generated for execution on a deep learning accelerator of artificial neural networks
AXM Chang, AT Zaidy, M Vitez, MC Glapa, A Chaurasia, E Culurciello
US Patent App. 17/092,040, 2022
22022
Deep neural networks compiler for a trace-based accelerator
AXM Chang, A Zaidy, M Vitez, L Burzawa, E Culurciello
Journal of Systems Architecture 102, 101659, 2020
22020
Accuracy and Performance Improvements in Custom CNN Architectures
A Zaidy
22016
Hardware accelerator for convolutional neural networks and method of operation thereof
E Culurciello, V Gokhale, A Zaidy, A Chang
US Patent 11,775,313, 2023
12023
Wafer-on-wafer formed memory and logic
SS Eilert, AT Zaidy, GE Hush, KR Parekh
US Patent App. 17/884,365, 2023
12023
Memory device for wafer-on-wafer formed memory and logic
GE Hush, SS Eilert, AT Zaidy, KR Parekh
US Patent App. 17/712,935, 2023
12023
Caching Techniques for Deep Learning Accelerator
AT Zaidy, PA Estep, DA Roberts
US Patent App. 17/146,314, 2022
12022
Wafer-on-wafer formed memory and logic for genomic annotations
SS Eilert, KR Parekh, AT Zaidy, GE Hush
US Patent 11,915,742, 2024
2024
Deep neural networks compiler for a trace-based accelerator
AXM Chang, A Zaidy, E Culurciello, M Vitez
US Patent 11,861,337, 2024
2024
Data migration schedule prediction using machine learning
DA Roberts, AT Zaidy
US Patent 11,829,627, 2023
2023
Deep learning acceleration with mixed precision
S Ma, AT Zaidy, D Werran
US Patent App. 17/807,274, 2023
2023
Deep learning acceleration with mixed precision
S Ma, AT Zaidy, D Werran
US Patent App. 17/807,298, 2023
2023
Deep learning acceleration with mixed precision
S Ma, AT Zaidy, D Werran
US Patent App. 17/807,290, 2023
2023
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