| Snowflake: An efficient hardware accelerator for convolutional neural networks V Gokhale, A Zaidy, AXM Chang, E Culurciello 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 145* | 2017 |
| Dynamic modeling and simulation of a PEM fuel cell: MATLAB and LabVIEW modeling approach A Zaidy, P Pokharkar, R Krishnan, D Sonawane 2014 1st international conference on non conventional energy (ICONCE 2014 …, 2014 | 18 | 2014 |
| Deep neural networks compiler for a trace-based accelerator (short WIP paper) AXM Chang, A Zaidy, L Burzawa, E Culurciello Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on …, 2018 | 15* | 2018 |
| Low cost electricity meter reading system using GSM AA Adhau, NM Patel, AT Zaidy, SL Patil, AS Deshpande 2013 International Conference on Energy Efficient Technologies for …, 2013 | 12 | 2013 |
| Computation and memory bandwidth in deep neural networks E Culurciello, A Zaidy, V Gokhale Medium 5, 1-4, 2017 | 6 | 2017 |
| Inference engine circuit architecture A Zaidy, AXM Chang, E Culurciello US Patent 11,675,624, 2023 | 5 | 2023 |
| Efficient compiler code generation for deep learning snowflake co-processor AXM Chang, A Zaidy, E Culurciello 2018 1st Workshop on Energy Efficient Machine Learning and Cognitive …, 2018 | 4 | 2018 |
| Compiler with an artificial neural network to optimize instructions generated for execution on a deep learning accelerator of artificial neural networks AXM Chang, AT Zaidy, M Vitez, MC Glapa, A Chaurasia, E Culurciello US Patent App. 17/092,040, 2022 | 3 | 2022 |
| Deep neural networks compiler for a trace-based accelerator AXM Chang, A Zaidy, M Vitez, L Burzawa, E Culurciello Journal of Systems Architecture 102, 101659, 2020 | 3 | 2020 |
| A high efficiency accelerator for deep neural networks A Zaidy, AXM Chang, V Gokhale, E Culurciello 2018 1st Workshop on Energy Efficient Machine Learning and Cognitive …, 2018 | 3 | 2018 |
| Accuracy and Performance Improvements in Custom CNN Architectures A Zaidy | 2 | 2016 |
| Memory device for wafer-on-wafer formed memory and logic GE Hush, SS Eilert, AT Zaidy, KR Parekh US Patent 12,112,792, 2024 | 1 | 2024 |
| Caching techniques for deep learning accelerator AT Zaidy, PA Estep, DA Roberts US Patent 12,094,531, 2024 | 1 | 2024 |
| Deep neural networks compiler for a trace-based accelerator AXM Chang, A Zaidy, E Culurciello, M Vitez US Patent 11,861,337, 2024 | 1 | 2024 |
| Hardware accelerator for convolutional neural networks and method of operation thereof E Culurciello, V Gokhale, A Zaidy, A Chang US Patent 11,775,313, 2023 | 1 | 2023 |
| Wafer-on-wafer formed memory and logic SS Eilert, AT Zaidy, GE Hush, KR Parekh US Patent App. 17/884,365, 2023 | 1 | 2023 |
| Compiler configurable to generate instructions executable by different deep learning accelerators from a description of an artificial neural network AXM Chang, AT Zaidy, E Culurciello, J Cummins, M Vitez US Patent App. 17/092,013, 2022 | 1 | 2022 |
| Design and development of wireless vitals monitoring system P Pokharkar, D Patil, A Zaidy, R Krishnan, K Gadre, DN Sonawane 2013 Texas Instruments India Educators' Conference, 1-7, 2013 | 1 | 2013 |
| Discovery of hardware characteristics of deep learning accelerators for optimization via compiler AT Zaidy, M Vitez, E Culurciello, J Cummins, AXM Chang US Patent 12,118,460, 2024 | | 2024 |
| Signal routing between memory die and logic die for mode based operations AT Zaidy, GE Hush, SS Eilert, KR Parekh US Patent 12,112,793, 2024 | | 2024 |
Eugenio CulurcielloPascaline Systems Inc.Подтвержден адрес электронной почты в домене pascalinesys.com
