| Test application time and volume compression through seed overlapping W Rao, I Bayraktaroglu, A Orailoglu Proceedings of the 40th annual Design Automation Conference, 732-737, 2003 | 73 | 2003 |
| IC Piracy Prevention via Design Withholding and Entanglement WR Soroush Khaleghi, Kai Da Zhao Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 821 - 826, 2015 | 58* | 2015 |
| Logic mapping in crossbar-based nanoarchitectures W Rao, A Orailoglu, R Karri IEEE Design & Test of Computers 26 (1), 68-77, 2009 | 46 | 2009 |
| Topology aware mapping of logic functions onto nanowire-based crossbar architectures W Rao, A Orailoglu, R Karri Proceedings of the 43rd Annual Design Automation Conference, 723-726, 2006 | 39 | 2006 |
| Toward future systems with nanoscale devices: Overcoming the reliability challenge W Rao, C Yang, R Karri, A Orailoglu Computer 44 (2), 46-53, 2011 | 34 | 2011 |
| Logic level fault tolerance approaches targeting nanoelectronics plas W Rao, A Orailoglu, R Karri 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-5, 2007 | 30 | 2007 |
| Virtual compression through test vector stitching for scan based designs W Rao, A Orailoglu 2003 Design, Automation and Test in Europe Conference and Exhibition, 104-109, 2003 | 29 | 2003 |
| Defect-tolerant logic mapping on nanoscale crossbar architectures and yield analysis Y Su, W Rao 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009 | 24 | 2009 |
| Fault tolerant approaches to nanoelectronic programmable logic arrays W Rao, A Orailoglu, R Karri 37th Annual IEEE/IFIP International Conference on Dependable Systems and …, 2007 | 24 | 2007 |
| Hardware obfuscation using strong pufs S Khaleghi, W Rao 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 321-326, 2018 | 22 | 2018 |
| Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance W Rao, A Orailoglu, R Karri 24th IEEE VLSI Test Symposium, 6 pp.-221, 2006 | 17 | 2006 |
| Fault tolerant arithmetic with applications in nanotechnology based systems W Rao, A Orailoglu, R Karri 2004 International Conferce on Test, 472-478, 2004 | 17 | 2004 |
| Selective hardening of nanopla circuits I Polian, W Rao 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008 | 16 | 2008 |
| Fault tolerant nanoelectronic processor architectures W Rao, A Orailoglu, R Karri Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 16 | 2005 |
| An stt-MRAM based strong PUF S Khaleghi, P Vinella, S Banerjee, W Rao 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016 | 15 | 2016 |
| Frugal linear network-based test decompression for drastic test cost reductions W Rao, A Orailoglu, G Su IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 15 | 2004 |
| A standard cell approach for MagnetoElastic NML circuits D Giri, M Vacca, G Causapruno, W Rao, M Graziano, M Zamboni Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014 | 14 | 2014 |
| Architectural-level fault tolerant computation in nanoelectronic processors W Rao, A Orailoglu, R Karri 2005 International Conference on Computer Design, 533-539, 2005 | 14 | 2005 |
| Towards fault tolerant parallel prefix adders in nanoelectronic systems W Rao, A Orailoglu Proceedings of the conference on Design, automation and test in Europe, 360-365, 2008 | 13 | 2008 |
| Fault identification in reconfigurable carry lookahead adders targeting nanoelectronic fabrics W Rao, A Orailoglu, R Karri Eleventh IEEE European Test Symposium (ETS'06), 63-68, 2006 | 13 | 2006 |
