Mu-Tien Chang
Title
Cited by
Cited by
Year
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
MT Chang, P Rosenfeld, SL Lu, B Jacob
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
2582013
DRAM refresh mechanisms, penalties, and trade-offs
IS Bhati, MT Chang, Z Chishti, SL Lu, B Jacob
IEEE Transactions on Computers 65 (1), 108-121, 2016
1152016
An Integrated Simulation Infrastructure for the Entire Memory Hierarchy: Cache, DRAM, Nonvolatile Memory, and Disk
J Stevens, P Tschirhart, MT Chang, I Bhati, P Enns, J Greensky, Z Chisti, ...
Intel® Technology Journal 17 (1), 2013
242013
System and method for using a truth table graphical function in a statechart
RO Aberg, V Raghavan, Y Ren
US Patent 8,798,971, 2014
17*2014
A 65nm low power 2T1D embedded DRAM with leakage current reduction
MT Chang, PT Huang, W Hwang
2007 IEEE International SOC Conference, 207-210, 2007
162007
A fully-differential subthreshold sram cell with auto-compensation
MT Chang, W Hwang
APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1771-1774, 2008
152008
Coordinated in-module RAS features for synchronous DDR compatible memory
MT Chang, D Niu, H Zheng, SY Lim, KIM Indong, J Choi
US Patent 10,592,114, 2020
102020
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control
MT Chang, PT Huang, W Hwang
2008 IEEE International SOC Conference, 175-178, 2008
102008
Thyristor-based device with trench dielectric material
A Horch, S Robins
US Patent 6,835,997, 2004
102004
System and method for operating a DRR-compatible asynchronous memory module
SY Lim, MT Chang, D Niu, H Zheng, KIM Indong
US Patent 10,810,144, 2020
92020
3-d stacked memory with reconfigurable compute logic
MT Chang, P Gera, D Niu, H Zheng
US Patent App. 15/143,248, 2017
92017
System architecture with memory channel DRAM FPGA module
H Zheng, MT Chang
US Patent 10,013,212, 2018
82018
Transaction-based hybrid memory module
MT Chang, H Zheng, D Niu
US Patent App. 14/947,145, 2017
82017
Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application
F Sala, C Hu, H Zheng, D Niu, MT Chang
US Patent 9,983,821, 2018
72018
Reliability-aware memory partitioning mechanisms for future memory technologies
D Niu, MT Chang, H Zheng
US Patent 9,696,923, 2017
72017
Asynchronous communication protocol compatible with synchronous DDR protocol
D Niu, MT Chang, H Zheng, SY Lim, KIM Indong, J Choi, C Hanson
US Patent 10,621,119, 2020
62020
HBM with in-memory cache manager
T Stocksdale, MT Chang, H Zheng
US Patent 10,180,906, 2019
62019
Hybrid memory module and transaction-based memory interface
D Niu, MT Chang, H Zheng
US Patent 9,971,511, 2018
62018
Systems and methods for write and flush support in hybrid memory
MT Chang, D Niu, H Zheng, H Nam, Y Cho, SY Lim
US Patent App. 15/669,851, 2018
52018
High performance transaction-based memory systems
MT Chang, H Zheng, L Yin
US Patent 9,904,635, 2018
52018
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