Christopher Pulte
Christopher Pulte
Verified email at cam.ac.uk - Homepage
Title
Cited by
Cited by
Year
Modelling the ARMv8 architecture, operationally: Concurrency and ISA
S Flur, KE Gray, C Pulte, S Sarkar, A Sezgin, L Maranget, W Deacon, ...
Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of …, 2016
1232016
Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8
C Pulte, S Flur, W Deacon, J French, S Sarkar, P Sewell
Proceedings of the ACM on Programming Languages 2 (POPL), 1-29, 2017
802017
ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS
A Armstrong, C Pulte, S Flur, I Stark, N Krishnaswami, P Sewell, ...
392019
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors
KE Gray, G Kerneis, D Mulligan, C Pulte, S Sarkar, P Sewell
Proceedings of the 48th International Symposium on Microarchitecture, 635-646, 2015
342015
Mixed-size concurrency: ARM, Power, C/C++ 11, and SC
S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ...
ACM SIGPLAN Notices 52 (1), 429-442, 2017
252017
Promising-ARM/RISC-V: a simpler and faster operational concurrency model
C Pulte, J Pichon-Pharabod, J Kang, SH Lee, CK Hur
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language …, 2019
122019
Detailed models of instruction set architectures: From pseudocode to formal semantics
A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, P Mundkur, ...
Proceedings of the 25th Automated Reasoning Workshop, 13, 2018
52018
Repairing and mechanising the JavaScript relaxed memory model
C Watt, C Pulte, A Podkopaev, G Barbier, S Dolan, S Flur, ...
arXiv preprint arXiv:2005.10554, 2020
42020
The sail instruction-set semantics specification language
KE Gray, P Sewell, C Pulte, S Flur, R Norton-Wright
Technical report published by Cambridge University, 2017
42017
The Semantics of Multicopy Atomic ARMv8 and RISC-V
C Pulte
University of Cambridge, 2019
22019
ARMv8-A system semantics: instruction fetch in relaxed architectures
B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ...
European Symposium on Programming, 626-655, 2020
2020
ARMv8-A system semantics: instruction fetch in relaxed architectures
S Ben, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ...
2020
The Sail instruction-set semantics specification language
A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, R Norton-Wright, ...
2019
Research data supporting “Mixed-size Concurrency: ARM, POWER, C/C++ 11, and SC”
S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ...
University of Cambridge, 2016
2016
An Axiomatic Semantics for Instruction Fetching
B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ...
The Flat Operational Model
C PULTE, S FLUR, W DEACON, JON FRENCH, S SARKAR, P SEWELL
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Articles 1–16