Steve Dai
Steve Dai
NVIDIA Research
Подтвержден адрес электронной почты в домене nvidia.com - Главная страница
Название
Процитировано
Процитировано
Год
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
712018
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs
Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ...
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
612018
Elasticflow: A complexity-effective approach for pipelining irregular loop nests
M Tan, G Liu, R Zhao, S Dai, Z Zhang
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 78-85, 2015
492015
Magnet: A modular accelerator generator for neural networks
R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
452019
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
S Dai, Y Zhou, H Zhang, E Ustun, EFY Young, Z Zhang
2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018
432018
Multithreaded pipeline synthesis for data-parallel kernels
M Tan, B Liu, S Dai, Z Zhang
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 718-725, 2014
352014
Flushing-enabled loop pipelining for high-level synthesis
S Dai, M Tan, K Hao, Z Zhang
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
332014
Celerity: An Open Source RISC-V Tiered Accelerator Fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
272017
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
262017
High-level synthesis for low-power design
Z Zhang, D Chen, S Dai, K Campbell
IPSJ Transactions on System LSI Design Methodology 8, 12-25, 2015
262015
Area-efficient pipelining for FPGA-targeted high-level synthesis
R Zhao, M Tan, S Dai, Z Zhang
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
192015
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis
NK Srivastava, S Dai, R Manohar, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
182017
High-Level Synthesis with Timing-Sensitive Information Flow Enforcement
Z Jiang, S Dai, GE Suh, Z Zhang
International Conference On Computer Aided Design (ICCAD), 2018
142018
Mapping-Aware Constrained Scheduling for LUT-Based FPGAs
M Tan, S Dai, U Gupta, Z Zhang
Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015
142015
A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation
S Dai, G Liu, Z Zhang
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
112018
Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ...
1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
112017
Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests
G Liu, M Tan, S Dai, R Zhao, Z Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
92017
Enabling Adaptive Loop Pipelining in High-Level Synthesis
S Dai, G Liu, R Zhao, Z Zhang
9*
Accelerating Chip Design With Machine Learning
B Khailany, H Ren, S Dai, S Godil, B Keller, R Kirby, A Klinefelter, ...
IEEE Micro 40 (6), 23-32, 2020
72020
Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning
S Dai, Z Zhang
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
72019
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