Fazal Hameed
Fazal Hameed
Post-doc at TU-Dresden
Verified email at tu-dresden.de - Homepage
Title
Cited by
Cited by
Year
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
F Hameed, L Bauer, J Henkel
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
402013
Reducing latency in an SRAM/DRAM cache hierarchy via a novel tag-cache architecture
F Hameed, L Bauer, J Henkel
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
242014
Performance and energy-efficient design of STT-RAM last-level cache
F Hameed, AA Khan, J Castrillon
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (6 …, 2018
222018
Design of high performance fpga based face recognition system
I Sajid, MM Ahmed, I Taj, M Humayun, F Hameed
Progress in Electromagnetic Research Symposium Proceeding, 504-510, 2008
222008
Dynamic thermal management in 3D multi-core architecture through run-time adaptation
F Hameed, MA Al Faruque, J Henkel
2011 Design, Automation & Test in Europe, 1-6, 2011
212011
Magnetic racetrack memory: From physics to the cusp of applications within a decade
R Bläsing, AA Khan, PC Filippou, C Garg, F Hameed, J Castrillon, ...
Proceedings of the IEEE 108 (8), 1303-1321, 2020
202020
Shiftsreduce: Minimizing shifts in racetrack memory 4.0
AA Khan, F Hameed, R Bläsing, SSP Parkin, J Castrillon
ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-23, 2019
202019
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores
F Hameed, L Bauer, J Henkel
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 77-82, 2013
182013
Dynamic cache management in multi-core architectures through run-time adaptation
F Hameed, L Bauer, J Henkel
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 485-490, 2012
172012
RTSim: A cycle-accurate simulator for racetrack memories
AA Khan, F Hameed, R Bläsing, S Parkin, J Castrillon
IEEE Computer Architecture Letters 18 (1), 43-46, 2019
162019
VAET-STT: Variation aware STT-MRAM analysis and design space exploration tool
SM Nair, R Bishnoi, MS Golanbari, F Oboril, F Hameed, MB Tahoori
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
142017
Architecting on-chip DRAM cache for simultaneous miss rate and latency reduction
F Hameed, L Bauer, J Henkel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
122015
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache
F Hameed, L Bauer, J Henkel
2013 International Conference on Hardware/Software Codesign and System …, 2013
122013
Architecting STT Last-Level-Cache for performance and energy improvement
F Hameed, MB Tahoori
2016 17th International Symposium on Quality Electronic Design (ISQED), 319-324, 2016
112016
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads
AA Khan, NA Rink, F Hameed, J Castrillon
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on …, 2019
92019
Efficient STT-RAM last-level-cache architecture to replace DRAM cache
F Hameed, C Menard, J Castrillon
Proceedings of the International Symposium on Memory Systems, 141-151, 2017
92017
Normally-off stt-mram cache with zero-byte compression for energy efficient last-level caches
F Oboril, F Hameed, R Bishnoi, A Ahari, H Naeimi, M Tahoori
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
92016
SHRIMP: Efficient instruction delivery with domain wall memory
J Multanen, P Jääskeläinen, AA Khan, F Hameed, J Castrillon
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
82019
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization
F Hameed, J Castrillon
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
72017
Nvmain extension for multi-level cache systems
AA Khan, F Hameed, J Castrillon
Proceedings of the Rapido'18 Workshop on Rapid Simulation and Performance …, 2018
62018
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Articles 1–20