Rangharajan Venkatesan
Rangharajan Venkatesan
Senior Research Scientist, NVIDIA
Verified email at nvidia.com - Homepage
Cited by
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Scnn: An accelerator for compressed-sparse convolutional neural networks
A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ...
ACM SIGARCH Computer Architecture News 45 (2), 27-40, 2017
MACACO: Modeling and Analysis of Circuits for Approximate Computing
R Venkatesan, A Agarwal, K Roy, A Raghunathan
Proceedings of the International Conference on Computer-Aided Design, 667-673, 2011
TapeCache: A High Density, Energy-efficient Cache based on Domain Wall Memory
R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ...
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Spin-transfer torque memories: Devices, circuits, and systems
X Fong, Y Kim, R Venkatesan, SH Choday, A Raghunathan, K Roy
Proceedings of the IEEE 104 (7), 1449-1488, 2016
Timeloop: A systematic approach to dnn accelerator evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
2019 IEEE international symposium on performance analysis of systems and …, 2019
DWM-TAPESTRI: An Energy-efficient All-Spin Cache using Domain wall Shift based Writes
R Venkatesan, M Sharad, K Roy, A Raghunathan
Proceedings of the Conference on Design, Automation and Test in Europe, 1825 …, 2013
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing
SG Ramasubramanian, R Venkatesan, M Sharad, K Roy, A Raghunathan
2014 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2014
Simba: Scaling deep-learning inference with multi-chip-module-based architecture
YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
Stag: Spintronic-tape architecture for gpgpu cache hierarchies
R Venkatesan, SG Ramasubramanian, S Venkataramani, K Roy, ...
ACM SIGARCH Computer Architecture News 42 (3), 253-264, 2014
Magnet: A modular accelerator generator for neural networks
R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
Spintastic: Spin-based stochastic logic for energy-efficient computing
R Venkatesan, S Venkataramani, X Fong, K Roy, A Raghunathan
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
A modular digital VLSI flow for high-productivity SoC design
B Khailany, E Krimer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ...
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
Multi-level Magnetic RAM using Domain-wall Shift for Energy-efficient, High-density Caches
M Sharad, R Venkatesan, A Raghunathan, K Roy
Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium …, 2013
Analog/mixed-signal hardware error modeling for deep learning inference
AS Rekhi, B Zimmer, N Nedovic, N Liu, R Venkatesan, M Wang, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
STAxCache: An approximate, energy efficient STT-MRAM cache
A Ranjan, S Venkataramani, Z Pajouhi, R Venkatesan, K Roy, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Cache design with domain wall memory
R Venkatesan, VJ Kozhikkottu, M Sharad, C Augustine, A Raychowdhury, ...
IEEE Transactions on Computers 65 (4), 1010-1024, 2015
A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm
B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
2019 Symposium on VLSI Circuits, C300-C301, 2019
Buffets: An efficient and composable storage idiom for explicit decoupled data orchestration
M Pellauer, YS Shao, J Clemons, N Crago, K Hegde, R Venkatesan, ...
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
Asymmetric underlapped sub-10-nm n-FinFETs for high-speed and low-leakage 6T SRAMs
AG Akkala, R Venkatesan, A Raghunathan, K Roy
IEEE Transactions on Electron Devices 63 (3), 1034-1040, 2016
Energy-efficient Many-core Processor for Recognition and Mining using Spin-based Memory
R Venkatesan, VK Chippa, C Augustine, K Roy, A Raghunathan
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale …, 2011
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