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Anton Tsertov, Tšertov
Anton Tsertov, Tšertov
Researcher of Computer Science, Tallinn University of Technology
Verified email at ttu.ee - Homepage
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Year
A suite of IEEE 1687 benchmark networks
A Tšertov, A Jutman, S Devadze, MS Reorda, E Larsson, FG Zadegan, ...
2016 IEEE International Test Conference (ITC), 1-10, 2016
532016
High-level modeling and testing of multiple control faults in digital systems
A Jasnetski, SA Oyeniran, A Tsertov, M Schölzel, R Ubar
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
152016
Calculation of LFSR seed and polynomial pair for BIST applications
A Jutman, A Tsertov, R Ubar
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and …, 2008
152008
Post-silicon validation of IEEE 1687 reconfigurable scan networks
A Damljanovic, A Jutman, G Squillero, A Tsertov
2019 IEEE European Test Symposium (ETS), 1-6, 2019
112019
Software-based self-test generation for microprocessors with high-level decision diagrams
R Ubar, A Tsertov, A Jasnetski, M Brik
2014 15th Latin American Test Workshop-LATW, 1-6, 2014
112014
On automatic software-based self-test program generation based on high-level decision diagrams
A Jasnetski, R Ubar, A Tsertov
2016 17th Latin-American Test Symposium (LATS), 177-177, 2016
102016
Software-based self-test generation for microprocessors with high-level decision diagrams
A Jasnetski, R Ubar, A Tsertov, M Brik
Proceedings of the Estonian Academy of Sciences 63 (1), 48, 2014
92014
IEEE 1687 compliant ecosystem for embedded instrumentation access and in-field health monitoring
A Tsertov, A Jutman, K Shibin, S Devadze
2018 IEEE AUTOTESTCON, 1-9, 2018
72018
FPGA-controlled PCBA power-on self-test using processor's debug features
B Du, E Sánchez, MS Reorda, JP Acle, A Tsertov
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
72016
Microprocessor-based system test using debug interface
S Devadze, A Jutman, A Tsertov, M Instenberg, R Ubar
2008 NORCHIP, 98-101, 2008
72008
Automated software-based self-test generation for microprocessors
A Jasnetski, R Ubar, A Tsertov
2017 MIXDES-24th International Conference" Mixed Design of Integrated …, 2017
62017
New fault models and self-test generation for microprocessors using high-level decision diagrams
A Jasnetski, J Raik, A Tsertov, R Ubar
2015 IEEE 18th International Symposium on Design and Diagnostics of …, 2015
62015
Soc and board modeling for processor-centric board testing
A Tsertov, R Ubar, A Jutman, S Devadze
2011 14th Euromicro Conference on Digital System Design, 575-582, 2011
62011
Microprocessor modeling for board level test access automation
S Devadze, A Jutman, A Tsertov, R Ubar
Proc. of 10th IEEE Workshop on RTL and High Level Testing, 154-159, 2009
52009
Teaching digital test with BIST analyzer
A Jutman, A Tsertov, A Tsepurov, I Aleksejev, R Ubar, HD Wuttke
2008 19th EAEEIE Annual Conference, 123-128, 2008
42008
BIST analyzer: A training platform for SoC testing
A Jutman, A Tsertov, A Tsepurov, I Aleksejev, R Ubar, HD Wuttke
2007 37th Annual Frontiers In Education Conference-Global Engineering …, 2007
42007
On-Chip Sensors Data Collection and Analysis for SoC Health Management
K Shibin, M Jenihhin, A Jutman, S Devadze, A Tsertov
2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2023
32023
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
A Damljanovic, A Jutman, M Portolan, E Sanchez, G Squillero, A Tsertov
2019 IEEE International Test Conference (ITC), 1-8, 2019
32019
High-level test data generation for software-based self-test in microprocessors
AS Oyeniran, A Jasnetski, A Tsertov, R Ubar
2017 6th Mediterranean Conference on Embedded Computing (MECO), 1-6, 2017
32017
Automatic soc level test path synthesis based on partial functional models
A Tsertov, R Ubar, A Jutman, S Devadze
2011 Asian Test Symposium, 532-538, 2011
32011
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