| Programmable Interrupt Routing in Multiprocessor Devices V Easwaran, TI Incorporated US Patent 20,150,212,955, 2015 | 20 | 2015 |
| Ensuring imaging subsystem integrity in camera based safety systems R Gulati, V Easwaran, MN Mody, PD Karandikar, PYA Shankar, A Dubey, ... US Patent 9,628,787, 2017 | 13 | 2017 |
| System and method for managing cache PD Karandikar, M Mody, H Sanghavi, V Easwaran, PYA Shankar, R Gulati, ... US Patent 9,430,393, 2016 | 8 | 2016 |
| Resolving ADAS imaging subsystem functional safety quagmire R Gulati, V Easwaran, P Karandikar, M Mody, P Shankar 2015 IEEE International Conference on Consumer Electronics (ICCE), 291-294, 2015 | 5 | 2015 |
| A unique non-intrusive approach to non-ate based cul-de-sac soc debug V Easwaran, V Bansal, G Shurtz, R Gulati, M Mody, P Karandikar, ... 2014 27th IEEE International System-on-Chip Conference (SOCC), 336-339, 2014 | 2 | 2014 |
| Re-configurable coherent event forwarding mechanism for multiprocessor systems V Easwaran, M Mody, P Shankar 2014 IEEE International Symposium on Signal Processing and Information …, 2014 | 1 | 2014 |
| Method to determine contrariety between architectures containing stratified memory mapped register sets V Easwaran, N Gulur, S Srirangapathi, M Mody, R Gulati, P Karandikar, ... 2014 Fifth International Symposium on Electronic System Design, 210-214, 2014 | 1 | 2014 |
| Understanding system level caching behavior in multimedia SoC P Karandikar, M Mody, H Sanghvi, V Easwaran, PS YA, R Gulati, ... 2014 International Conference on Communication and Signal Processing, 317-320, 2014 | 1 | 2014 |
| Power management integrated circuit (pmic) power supply monitoring without external monitoring circuitry A Aneja, VK Easwaran, R Gulati US Patent App. 18/457,066, 2024 | | 2024 |
| Package On Package Memory Interface and Configuration With Error Code Correction R Gulati, A Dubey, N Vyagrheswarudu, V Easwaran, PD Karandikar, ... US Patent App. 18/306,510, 2023 | | 2023 |
| Package on package memory interface and configuration with error code correction R Gulati, A Dubey, N Vyagrheswarudu, V Easwaran, PD Karandikar, ... US Patent 11,662,211, 2023 | | 2023 |
| Package on package memory interface and configuration with error code correction R Gulati, A Dubey, N Vyagrheswarudu, V Easwaran, PD Karandikar, ... US Patent 10,767,998, 2020 | | 2020 |
| Package on package memory interface and configuration with error code correction R Gulati, A Dubey, N Vyagrheswarudu, V Easwaran, PD Karandikar, ... US Patent 10,089,172, 2018 | | 2018 |
| Efficient system level cache architecture for multimedia SoC P Karandikar, M Mody, H Sanghvi, V Easwaran, PS YA, R Gulati, ... 2014 International Conference on Advances in Computing, Communications and …, 2014 | | 2014 |
