| TEAM: Threshold adaptive memristor model S Kvatinsky, EG Friedman, A Kolodny, UC Weiser IEEE transactions on circuits and systems I: regular papers 60 (1), 211-221, 2012 | 935 | 2012 |
| MAGIC—Memristor-aided logic S Kvatinsky, D Belousov, S Liman, G Satat, N Wald, EG Friedman, ... IEEE Transactions on Circuits and Systems II: Express Briefs 61 (11), 895-899, 2014 | 873 | 2014 |
| MMX technology extension to the Intel architecture A Peleg, U Weiser IEEE micro 16 (4), 42-50, 1996 | 830 | 1996 |
| Memristor-based material implication (IMPLY) logic: Design principles and methodologies S Kvatinsky, G Satat, N Wald, EG Friedman, A Kolodny, UC Weiser IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (10 …, 2013 | 693 | 2013 |
| Interconnect-power dissipation in a microprocessor N Magen, A Kolodny, U Weiser, N Shamir Proceedings of the 2004 international workshop on System level interconnect …, 2004 | 598 | 2004 |
| MRL—Memristor ratioed logic S Kvatinsky, N Wald, G Satat, A Kolodny, UC Weiser, EG Friedman 2012 13th International Workshop on Cellular Nanoscale Networks and their …, 2012 | 352 | 2012 |
| Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors TY Morad, UC Weiser, A Kolodnyt, M Valero, E Ayguade IEEE Computer Architecture Letters 5 (1), 14-17, 2006 | 299 | 2006 |
| Intel MMX for multimedia PCs A Peleg, S Wilkie, U Weiser Communications of the ACM 40 (1), 24-38, 1997 | 286 | 1997 |
| Dynamic flow instruction cache memory organized around trace segments independent of virtual address line A Peleg, U Weiser US Patent 5,381,533, 1995 | 265 | 1995 |
| Memristor-based IMPLY logic design procedure S Kvatinsky, A Kolodny, UC Weiser, EG Friedman 2011 IEEE 29th International Conference on Computer Design (ICCD), 142-147, 2011 | 197 | 2011 |
| Correlated load-address predictors M Bekerman, S Jourdan, R Ronen, G Kirshenboim, L Rappoport, A Yoaz, ... ACM SIGARCH Computer Architecture News 27 (2), 54-63, 1999 | 150 | 1999 |
| Many-core vs. many-thread machines: Stay away from the valley Z Guz, E Bolotin, I Keidar, A Kolodny, A Mendelson, UC Weiser IEEE Computer Architecture Letters 8 (1), 25-28, 2009 | 143 | 2009 |
| Semantic locality and context-based prefetching using reinforcement learning L Peled, S Mannor, U Weiser, Y Etsion Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 129 | 2015 |
| A wavefront notation tool for VLSI array design U Weiser, AL Davis VLSI Systems and Computations, 226-234, 1981 | 118 | 1981 |
| A resistive CAM processing-in-storage architecture for DNA sequence alignment R Kaplan, L Yavits, R Ginosar, U Weiser IEEE Micro 37 (4), 20-28, 2017 | 97 | 2017 |
| The desired memristor for circuit designers S Kvatinsky, EG Friedman, A Kolodny, UC Weiser IEEE Circuits and Systems Magazine 13 (2), 17-22, 2013 | 96 | 2013 |
| Models of memristors for SPICE simulations S Kvatinsky, K Talisveyberg, D Fliter, A Kolodny, UC Weiser, EG Friedman 2012 IEEE 27th Convention of electrical and electronics engineers in Israel, 1-5, 2012 | 95 | 2012 |
| Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction UC Weiser, D Perlmutter, Y Yaari US Patent 5,265,213, 1993 | 90 | 1993 |
| Branch prediction and resolution apparatus for a superscalar computer processor ET Grochowski, DB Alpert, JD Mills, UC Weiser US Patent 5,442,756, 1995 | 79 | 1995 |
| Robust quantization: One model to rule them all B Chmiel, R Banner, G Shomron, Y Nahshan, A Bronstein, U Weiser Advances in neural information processing systems 33, 5308-5317, 2020 | 77 | 2020 |
